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W83791D/W83791G Winbond H/W Monitoring IC
W83791D/G
W83791D/W83791G Data Sheet Revision History
PAGES DATES VERSION VERSION ON WEB MAIN CONTENTS
1 2 3
n.a. n.a. P.7 P.34 P.43/44 01/Jan 01/Jan 0.5 0.51
n.a. n.a. n.a.
All version before 0.50 are for internal use. First publication. (1) Revise SLOTOCC# pin description. (2) Add SMI# /IRQ for Voltage/Fan description. Register Index 1Ah~1Fh revised. This update is for C version IC. 1) Add EVNTRAP1-5 polarity (Index Ah ) 2) Add VID protection control bit (Index15h bit5) 3) Add FAN1-3/PWMOUT1-3 as GPIn data register. (Index 95h/97h) 4) SMARTFANTM step up/down time registers exchanged. 5) Add a bit (Index A6 bit7) to know either speech or GPIO function did you use. 6) Pin44 (SMI#/LEDOUT) is a multifunction, it is programmable. 7) EVENTRAP can as GPIO by programming Index A6h bit0-4 . 8) Updated V0.17 schematics adding LEDOUT circuit for SMI# (Pin 44) Repaginate datasheet Change all version include version on web to 1.0 Add lead-free package version
4 5
01/Mar 01/May
0.6 0.7
n.a. n.a.
P. 40 P. 42 P. 60/61 P. 58/59 P. 66 P. 66 P. 66 P. 87 6 7 8 All pages n.a. n.a. 01/Aug 02/Apr 06/Apr 0.71 1.0 1.1 n.a. 1.0 1.1
Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this data sheet belong to their respective owners.
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Publication Release Date: April 14, 2006 Revision 1.1
W83791D/G
Table of Contents1. 2. GENERAL DESCRIPTION............................................................................................................ 1 FEATURES.................................................................................................................................... 3 2.1 Monitoring Items .................................................................................................................. 3 2.2 Address Resolution Protocol (ARP) and Alert-Standard Forum (ASF) ............................... 3 2.3 Speech Items ....................................................................................................................... 3 2.4 Actions Enabling .................................................................................................................. 3 2.5 Enhance Monitoring VID function ........................................................................................ 4 2.6 General ................................................................................................................................ 4 2.7 Package ............................................................................................................................... 4 KEY SPECIFICATIONS................................................................................................................. 4 PIN CONFIGURATION.................................................................................................................. 5 PIN DESCRIPTION ....................................................................................................................... 6 FUNCTION DESCRIPTION ........................................................................................................ 11 6.1 General Description ........................................................................................................... 11 6.2 Access Interface ................................................................................................................ 11
6.2.1 The first serial bus access timing .......................................................................................11 General Description............................................................................................................12 Event Trigger Queue ..........................................................................................................12 Connection of EEPROM.....................................................................................................14 Speaker Output ..................................................................................................................14
3. 4. 5. 6.
6.3
Speech Function ................................................................................................................ 12
6.3.1 6.3.2 6.3.3 6.3.4
6.4 6.5 6.6
Address Resolution Protocol (ARP) Introduction............................................................... 15 ASF (Alert Standard Format) Introduction ......................................................................... 17
6.5.1 6.6.1 6.6.2 Platform Event Trap (PET) .................................................................................................17 Monitor over 4.096V voltage:..............................................................................................20 Monitor negative voltage: ...................................................................................................20 Fan speed count.................................................................................................................21 Fan speed control...............................................................................................................22 Smart Fan Control ..............................................................................................................23 Monitor temperature from thermistor: .................................................................................25 Monitor temperature from Pentium IITM thermal diode or bipolar transistor 2N3904 .........25 SMI# interrupt for W83791D Voltage..................................................................................25 SMI# interrupt for W83791D Fan........................................................................................26 SMI# interrupt for W83791D/G temperature sensor 1/2/3 ..................................................26 Over-Temperature (OVT#) for W83791D/G temperature sensor 1/2/3...............................27
Analog Inputs ..................................................................................................................... 19
6.7
FAN Speed Count and FAN Speed Control ...................................................................... 21
6.7.1 6.7.2 6.7.3
6.8
Temperature Measurement Machine................................................................................. 24
6.8.1 6.8.2 6.8.3 6.8.4 6.8.5 6.8.6
7.
CONTROL AND STATUS REGISTER........................................................................................ 29 7.1 Speech Flash Memory Address Registers Index 00h-02h (Bank 0)............................. 29 7.2 Speech Flash Memory Data Registers Index 03h-06h (Bank 0) .................................. 29 7.3 Speech Flash Memory Control Register Index 07h (Bank 0)........................................ 29 7.4 Event Trigger Timeout Register Index 08h (Bank 0)..................................................... 30 Publication Release Date: April 14, 2006 Revision 1.1
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W83791D/G
7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 7.17 7.18 7.19 7.20 7.21 7.22 7.23 7.24 7.25 7.26 7.27 7.28 7.29 7.30 7.31 7.32 7.33 7.34 7.35 7.36 7.37 7.38 7.39 7.40 7.41 7.42 7.43 7.44 7.45 7.46 Speech Programmable Trigger Register Index 09h (Bank 0) ....................................... 30 Speech Input Trigger Property Register Index 0Ah (Bank 0) ....................................... 31 Reserved Register Index 0Bh (Bank 0)......................................................................... 31 VID and VCORE voltage Property Register Index 0Ch (Bank 0) ................................. 31 Speech Flash Memory Read Data Registers Index 0Dh-0Eh (Bank 0)........................ 31 Reserved Register Index 0Fh (Bank 0)......................................................................... 31 VID Control/Status Register Index 10h (Bank 0) .......................................................... 31 Entry Disable VID Output Control Register Index 11h (Bank 0) ................................... 32 VID Output Tolerance/Limit Register Index 12h (Bank 0)............................................. 32 GPIO Control Register I Index 13h (Bank 0)................................................................. 32 GPIO Data/Status Register I Index 14h (Bank 0) ......................................................... 33 GPIO Control Register II Index 15h (Bank 0)................................................................ 33 GPIO Output Data and Status Register II Index 16h (Bank 0) ..................................... 34 LED Control Register Index 17h (Bank 0)..................................................................... 34 User Defined Registers Index 18h-1Ch (Bank 0).......................................................... 35 Speech Control Register 1 Index 1Dh (Bank 0)............................................................ 35 Speech Control Register 2 Index 1Eh (Bank 0) ............................................................ 36 Speech Control Register 3 Index 1Fh (Bank 0) ............................................................ 36 Value RAM Index 20h- 3Fh (Bank 0) ............................................................................ 37 Configuration Register Index 40h (Bank 0) ................................................................... 38 Interrupt Status Register 1 Index 41h (Bank 0)............................................................. 39 Interrupt Status Register 2 Index 42h (Bank 0)............................................................. 39 SMI# Mask Register 1 Index 43h (Bank 0) ................................................................... 40 SMI# Mask Register 2 Index 44h (Bank 0) ................................................................... 40 IRQ Mask Register 1 Index 45h (Bank 0) ..................................................................... 41 IRQ Mask Register 2 Index 46h (Bank 0) ..................................................................... 41 VID/Fan Divisor Register Index 47h (Bank 0) ............................................................... 42 Serial Bus Address Register Index 48h (Bank 0).......................................................... 42 Voltage ID (VID4) & Device ID Index 49h (Bank 0) ...................................................... 42 Temperature 2 and Temperature 3 Serial Bus Address Register Index4Ah (Bank 0).. 43 Pin Control Register Index4Bh (Bank 0) ....................................................................... 43 SMI#/OVT# Property Select Index 4Ch (Bank 0).......................................................... 44 FAN 1- 3 IN/OUT and BEEP Control Register Index 4Dh (Bank 0)............................. 45 Bank Select Index 4Eh (Bank 0) ................................................................................... 46 Winbond Vendor ID Index 4Fh (Bank 0) ....................................................................... 46 Winbond Test Register Index 50h - 55h (Bank 0)......................................................... 46 BEEP Control Register 1 Index 56h (Bank 0) ............................................................... 46 BEEP Control Register 2 Index 57h (Bank 0) ............................................................... 47 Chip ID Index 58h (Bank 0).......................................................................................... 47 Diode Selection Register Index 59h (Bank 0) ............................................................... 47 Reserved Index 5Ah - (Bank 0).................................................................................... 48 FANIN 4/5 Control Index 5Bh (Bank 0) ......................................................................... 48 Publication Release Date: April 14, 2006 Revision 1.1
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W83791D/G
7.47 FAN 4/5 Divisor Control Index 5Ch (Bank 0) ................................................................ 48 7.48 VBAT Monitor Control Register Index 5Dh (Bank 0)..................................................... 49 7.49 ACPI Temperature Increment Register Index 5Eh ....................................................... 49 7.50 Reserved Index 5Fh (Bank 0) ....................................................................................... 50 7.51 FAN 1 Pre-Scale Register Index 80h (Bank 0) ............................................................. 50 7.52 FAN 1 Duty Cycle Select Register 81h (Bank 0) .......................................................... 50 7.53 FAN 2 Pre-Scale Register Index 82h (Bank 0) ............................................................. 51 7.54 FAN2 Duty Cycle Select Register Index 83h (Bank 0).................................................. 51 7.55 FAN 1/2 Configuration Register Index 84h (Bank 0)..................................................... 51 7.56 Fan 1 Target Temperature Register/Target Fan 1 Speed Control Register Index 85h (Bank 0) ....................................................................................................................................... 52 7.57 Fan 2 Target Temperature Register/Target Fan 2 Speed Control Register Index 86h (Bank 0) ....................................................................................................................................... 53 7.58 Tolerance of Fan1/2 Target Temperature or Speed Register Index 87h (Bank0) ........ 53 7.59 Fan 1 PWM Stop Duty Cycle Register Index 88h (Bank 0) .......................................... 54 7.60 Fan 2 PWM Stop Duty Cycle Register 89h (Bank 0) .................................................... 54 7.61 Fan 1 Start-up Duty Cycle Register Index 8Ah (Bank 0) .............................................. 54 7.62 Fan 2 Start-up Duty Cycle Register Index 8Bh (Bank 0) .............................................. 54 7.63 Fan 1 Stop Time Register Index 8Ch (Bank 0) ............................................................. 54 7.64 Fan 2 Stop Time Register Index 8Dh (Bank 0) ............................................................. 55 7.65 Fan 1/2/3 Step Down Time Register Index 8Eh (Bank 0) ............................................. 55 7.66 Fan 1/2/3 Step Up Time Register Index 8Fh (Bank 0).................................................. 55 7.67 Temperature Sensor 1 (VTIN1) Offset Register Index 90h (Bank 0)............................ 55 7.68 Temperature Sensor 2 (VTIN2) Offset Register Index 91h (Bank 0)............................ 56 7.69 Temperature Sensor 3 (VTIN3) Offset Register Index 92h (Bank 0)............................ 56 7.70 FAN 3 Pre-Scale Register Index 93h (Bank 0) ............................................................. 57 7.71 FAN 3 Duty Cycle Select Register Index 94h (Bank 0)................................................. 57 7.72 FAN 3 Configuration Register Index 95h (Bank 0)........................................................ 58 7.73 Fan 3 Target Temperature Register/Target Fan 3 Speed Control Register Index 96h (Bank 0) ....................................................................................................................................... 58 7.74 Tolerance of Fan 3 Target Temperature or Speed Register Index 97h (Bank 0) ......... 59 7.75 Fan 3 PWM Stop Duty Cycle Register Index 98h (Bank 0) .......................................... 59 7.76 Fan 3 Start-up Duty Cycle Register Index 99h (Bank 0)............................................... 60 7.77 Fan 3 Stop Time Register Index 9Ah (Bank 0) ............................................................. 60 7.78 Interrupt Status Register III Index 9Bh (Bank 0) ........................................................... 60 7.79 SMI# Mask Register III Index 9Ch (Bank 0).................................................................. 61 7.80 Interrupt Mask Register III Index 9Dh (Bank 0)............................................................. 61 7.81 FAN4_PRE_SCALE register Index 9Eh (Bank 0)......................................................... 62 7.82 FAN5_PRE_SCALE register Index 9Fh (Bank 0) ......................................................... 62 7.83 FAN 4 Duty Cycle Select Register--A0h (Bank 0) ............................................................ 63 7.84 FAN 5 Duty Cycle Select Register--A1h (Bank 0) ............................................................ 63 7.85 BEEP Control Register 3 Index A3h (Bank 0)............................................................... 63 Publication Release Date: April 14, 2006 Revision 1.1
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W83791D/G
7.86 Speech Flash Memory Read Data Registers Index A4h-A5h (Bank 0) ........................ 64 7.87 EVNTRAP1- 5 and GPIO 5-9 Select Index A6h (Bank 0)............................................. 64 7.88 Flash Page count Index A7h (Bank 0) .......................................................................... 65 7.89 Real Time Hardware Status Register I Index A9h (Bank 0).......................................... 65 7.90 Real Time Hardware Status Register II Index AAh (Bank 0) ........................................ 65 7.91 Real Time Hardware Status Register III Index ABh (Bank 0) ....................................... 66 7.92 Revered Index AC - AFh (Bank 0) ................................................................................ 67 7.93 Value RAM 2 Index B0h - B7h (BANK 0) ...................................................................... 67 7.94 Temperature Sensor 2 Temperature (High Byte) Register Index C0h (Bank 0)........... 67 7.95 Temperature Sensor 2 Temperature (Low Byte) Register Index C1h (Bank 0)............ 67 7.96 Temperature Sensor 2 Configuration Register Index C2h (Bank 0) ............................. 68 7.97 Temperature Sensor 2 Hysteresis (High Byte) Register Index C3h (Bank 0)............... 68 7.98 Temperature Sensor 2 Hysteresis (Low Byte) Register Index C4h (Bank 0) ............... 68 7.99 Temperature Sensor 2 Over-temperature (High Byte) Register Index C5h (Bank 0)... 68 7.100 Temperature Sensor 2 Over-temperature (Low Byte) Register Index C6h (Bank 0).... 68 7.101 Temperature Sensor 3 Temperature (High Byte) Register Index C8h (Bank 0)........... 69 7.102 Temperature Sensor 3 Temperature (Low Byte) Register Index C9h (Bank 0)............ 69 7.103 Temperature Sensor 3 Configuration Register Index CAh (Bank 0)............................. 69 7.104 Temperature Sensor 3 Hysteresis (High Byte) Register Index CBh (Bank 0) .............. 69 7.105 Temperature Sensor 3 Hysteresis (Low Byte) Register Index CCh (Bank 0)............... 69 7.106 Temperature Sensor 3 Over-temperature (High Byte) Register Index CDh (Bank 0) .. 70 7.107 Temperature Sensor 3 Over-temperature (Low Byte) Register Index CEh (Bank 0) ... 70 ARP (ADDRESS RESOLUTION PROTOCOL) USE REGISTER DEFINED.............................. 71 8.1 Unique Device Identifier (UDID) -- 20h-2Fh (Bank 1)........................................................ 71 8.2 ASF Sensor Environmental Event ..................................................................................... 72
8.2.1 8.2.2 8.2.3 8.2.4 Temperature: Get Event Data message .............................................................................72 Voltage: Get Event Data message .....................................................................................75 Fan: Get Event Data message ...........................................................................................77 Case Intrusion: Get Event Data message ..........................................................................79 ASF Upper/Lower Temperature Registers: ........................................................................80 Sensor device: (SMBus Address, Read/Write)...................................................................81 Relative Entity ID Table: .....................................................................................................81 Entity Instance Register......................................................................................................82
8.
8.3
ASF Response Registers Index 40h-7Fh (Bank 1)...................................................... 80
8.3.1 8.3.2 8.3.3 8.3.4
9.
8.4 BJT RT-Table - 50h-57h (Bank 7) TEST mode only..................................................... 82 ELECTRICAL CHARACTERISTICS ........................................................................................... 83 9.1 Absolute Maximum Ratings ............................................................................................... 83 9.2 DC Characteristics ............................................................................................................. 83 9.3 AC Characteristics ............................................................................................................. 85
9.3.1 Serial Bus Timing Diagram.................................................................................................85
10. 11.
HOW TO READ THE TOP MARKING ........................................................................................ 86 PACKAGE SPECIFICATION....................................................................................................... 87
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Publication Release Date: April 14, 2006 Revision 1.1
W83791D/G
1. GENERAL DESCRIPTION
W83791D/G is an evolving version of the W83782D/G --- Winbond's most popular hardware status monitoring IC. Besides the conventional functions of W83782D/G, W83791D/G uniquely provides several innovative features such as speech function, ASF sensor compliant, SMBus 2.0 ARP command compatible, VID table selection trapping, and 5VID output control. Conventionally, W83791D/G can be used to monitor several critical hardware parameters of the system, including power supply voltages, fan speeds, and temperatures, which are very important for a high-end computer system to work stably and efficiently. As for data access, W83791D/G provides slave SMBus 2.0 interface which can reply PEC (Packet Error Code) when as ASF sensor. An 8-bit analog-to-digital converter (ADC) was built inside W83791D/G. W83791D/G can simultaneously monitor 10 analog voltage inputs (including power VDD/5VSB monitoring), 5 fan tachometer inputs, 3 remote temperatures, and one case open detection signal. The sense of remote temperature can be performed by thermistors, 2N3904 NPN-type transistors, or directly from IntelTM CPU with thermal diode output. W83791D/G provides 3 PWM (pulse width modulation) outputs for two modes of smart fan control- Thermal CruiseTM mode and Speed Cruise mode. Under Thermal mode, temperatures of CPU and the system can be maintained within specific CruiseTM programmable ranges under the hardware control. Speed Cruise , namely, is to keep the fan operate in the specific programmable r.p.m. As for warning mechanism, W83791D/G provides speech voice warning, beep tone warning, and SMI#, OVT#, IRQ signals for system protection events. Additionally, 5 VID inputs are provided to read the VID of CPU (i.e. PentiumTM II/III) if applicable. These VID inputs provide the information of Vcore voltage that CPU expects. Furthermore, W83791D/G provides programmable VID output control to alter the voltage CPU consumes. W83791D/G also uniquely provides an optional feature: early stage (before BIOS was loaded) beep / speech warning to detect if the fatal elements present --- Vcore or +3.3V voltage fail and thus the system can not be boomed up. If the VSB power on setting refers to Intel VRM 9.x, the VID table within W83791D/G will be according to the new one. W83791D/G also has 2 specific pins to provide selectable address setting for application of multiple devices (up to 4 devices) wired through I2CTM interface. W83791D/G speech function is enabled by building in a programmable speech synthesizer with a 9-bit current DAC output as well as a connectable external flash memory for storing voice data. W83791D/G supports 1 CPU present or absent event trap, 5 external event traps, 17 hardware monitor event traps (10 analog voltage, 3 fan tachometer, 3 remote temperature, 1 case open) and 128 internal programmable event traps, amounting to 151 different speech outputs. If more than two events happen simultaneously, the priority set is: SLOTOCC# > EVNTRP1 > EVNTRP2 > EVNTRP3 > EVNTRP4 > EVNTRP5 > 128 Programmable events (Bank0 index 09h) > 17 Hardware status events. Voice data stored in the external flash memory interface with Winbond W55FXX is flexible to change by Winbond application software and on-line programming flash data is provided also. Besides, an external resistor is added to provide ring oscillator. When you do not use the speech function, W83791D/G provides a set of flexible I/O control functions to the system designer through a set of General Purpose I/O ports. These GPIO ports may serve as simple I/O or may be individually configured to provide a pre-defined alternate function. If pin 9 (SPEECH_SEL) is trapped to high at VSB power on, this function will be active.
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Publication Release Date: April 14, 2006 Revision 1.1
W83791D/G
W83791D/G can uniquely serve as an ASF sensor to respond to ASF master's request for the implementation of network management in OS-absent state. Through W83791D/G compliance with ASF sensor spec, network server is able to monitor the environmental status of the client in OS-absent state by PET frame values returned from W83791D/G, such as temperatures, voltages, fan speed, and case open. Moreover, W83791D/G supports SMBus 2.0 ARP command to solve the problem of address conflicts by dynamically assigning a new unique address to W83791D/G after W83791D/G's UDID is sent. Through the application software or BIOS, the users can read all the monitored parameters of the system from time to time. A pop-up warning can also be activated when the monitored item is out of the proper/preset range. The application software could be Winbond's Hardware DoctorTM, IntelTM LDCM (LanDesk Client Management), or other management application software. Besides, the users can set up the upper and lower limits (alarm thresholds) of these monitored parameters and activate one programmable and maskable interrupts. An optional beep tone could be used as a warning signal when the monitored parameters are out of the preset range.
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Publication Release Date: April 14, 2006 Revision 1.1
W83791D/G
2. FEATURES 2.1 Monitoring Items
* 10 voltage inputs --- Typical for VCORE, +3.3V, +12V, -12V, +5V, -5V, +5VSB, VBAT, and two reserved * 5 fan speed monitoring inputs * 3 temperature inputs from remote thermistors, 2N3904 NPN-type transistors or PentiumTM II (Deschutes) thermal diode output * Case open detection input * WATCHDOG comparison of all monitored values * Programmable hysteresis and setting points (alarm thresholds) for all monitored items
2.2
* * * * *
Address Resolution Protocol (ARP) and Alert-Standard Forum (ASF)
Support System Management Bus (SMBus) version 2.0 specification Comply with hardware sensor slave ARP (Address Resolution Protocol) Response sensor type ARP command Response ASF command --- Get Event Data , Get Event Status Comply with ASF sensors (Monitoring fan speed, voltage, temperature, and case open)
2.3
* * * * * * * * * *
Speech Items
Programmable speech synthesizer with new high fidelity synthesis algorithm Build in 8-bit current D/A converter 1 CPU present or absent trigger input 5 External trigger inputs 128 Internal programmable trigger inputs 17 H/W Monitor event trigger inputs Programmable 0-255 seconds timeout trigger inputs for firmware or software Instruction cycle is <= 400 uS typically Section control provided in each voice section External resistor for ring oscillator
2.4
Actions Enabling
* Beep tone warning separated speech output * 5 PWM (pulse width modulation) outputs for fan speed control (1~3 support Smart Fan control) and 5 Fan speed inputs for monitoring --- Total up to 5 sets of fan speed monitoring and controlling * Issue SMI#, OVT#, IRQ signals to activate system protection * Warning signal pop-up in application software
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Publication Release Date: April 14, 2006 Revision 1.1
W83791D/G
2.5 Enhance Monitoring VID function
* CPU Voltage ID reading * VID output control * Enhance beep warning by detecting Intel VRM 9.0 VID
2.6
* * * *
2
General
TM
I C serial bus interface 5 VID input pins for CPU VCORE identification (for PentiumTM II/III) Initial power fault beep (for +3.3V, VCORE) 2 pins (A0, A1) to provide selectable address setting for application of multiple devices (up to 4 devices) wired through I2CTM interface Winbond hardware monitoring application software (Hardware DoctorTM ) support, for both Windows 95/98/2000 and Windows NT 4.0/5.0 * Internal clock Oscillator with 3M Hz * 5V VSB operation
2.7
Package
* 48-pin LQFP
3. KEY SPECIFICATIONS
* Voltage monitoring accuracy * Intel VRM 9.x Voltage monitoring accuracy * Monitoring Temperature Range and Accuracy - 40C to +120C * Supply Voltage * Operating Supply Current * ADC Resolution 1% (Max) 0.5% (Max) 3C(Max) 5V 5 mA typ. 8 Bits
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Publication Release Date: April 14, 2006 Revision 1.1
W83791D/G
4. PIN CONFIGURATION
V V+ C I 3.3 O NV RRI E0N V I N R 1 + 12 V I N 12 V I N + 5 V S B 5 V I N
V B A T
G N D A
B E E P
V I D 3
36
35
34
33
32 31
30
29
28
27
26
25 24 23 22 21 20
VREF VTIN3/PIITD3 VTIN2/PIITD2 VTIN1/PIITD1 VID0 OVT# IRQ/GPIO10 SMI#/LED EVNTRP1/GPIO5 EVNTRP2/GPIO6/FANIN4 EVNTRP3/GPIO7/FANIN5 EVNTRP4/GPIO8/PWMOUT4
37 38 39 40 41 42 43 44 45 46 47 48 1 2 3 4 5 6 7 8 9 10 11
W83791D
19 18 17 16 15 14 13 12
VIDIN2 PWMTOUT3/VID_V90 SDA SC L FANIN1 FANIN2 FANIN3 VID4 CASEOPEN SLOTOCC# GNDD VDD
EERACD V OEDL A NPXDKT T T ROA R / U/ P GTG 5 P/ P / I GI G OPO P 0I2 I O O 1 9 / P W M O U T 5
C T R L / G P I O 3
M O D E / G P I O 4
S P E A K E R / L E D / S P E E C H _ S E L
P W M O U T 1 / A 0
P W M O U T 2 / A 1
V I D 1
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W83791D/G
5. PIN DESCRIPTION
I/O12t - TTL level bi-directional pin with 12 mA source-sink capability I/O12ts - TTL level and schmitt trigger with 12 mA source-sink capability I/O8ts - TTL level and schmitt trigger with 8 mA source-sink capability I/O6ts - TTL level and schmitt trigger with 6 mA source-sink capability I/OD12ts - TTL level and schmitt trigger open drain output with 12 mA sink capability OUT12 - Output pin with 12 mA source-sink capability OD12 - Open-drain output pin with 12 mA sink capability AOUT - Output pin (Analog) INt - TTL level input pin INts - TTL level input pin and schmitt trigger AIN - Input pin (Analog)
PIN NAME
PIN NO.
TYPE
DESCRIPTION
EVNTRP5 / GPIO9/ PWMOUT5
1
I/O 1 2 t
Event trapping to selection speech output sound. Default is high edge trigger. General purpose I/O function. If pin 9 (SPEECH_SEL) is trapped to high at VSB power on, this function will be active. The I/O control and status is defined in BANK0 Index 13h~14h. Otherwise, GPIO pin or PWMOUT Fan control can be selected by registers, but the PWMOUT can not support Smart Fan.
EOP GPIO11
2
I I/OD12ts
End of Process signal input from cascaded Flash. General purpose I/O function pin. If pin 9 (SPEECH_SEL) is trapped to high at VSB power on, this function will be active. Resistor (Rosc) connect to VSB used to adjust ring oscillator frequency. Speech address pulse output, connect to W55FXX. When this pin translates from logic high to logic low, it will latch the data pin 6 and shift it into a speech flash address counter. General purpose I/O function. If pin 9 (SPEECH_SEL) is trapped to high at VSB power on, this function will be active. Speech clock output, for speech data read-out and write-in, connect to W55FXX. When this pin translates from logic high to logic low, the data pin 6 will be latched by this clock. General purpose I/O function. If pin 9 (SPEECH_SEL) is trapped to high at VSB power on, this function will be active.
REXT ADDR /
3 4
I OUT12
GPIO0
I/OD12ts
CLKOUT /
5
OUT12
GPIO1
I/OD12ts
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W83791D/G
PIN DESCRIPTION, continued
PIN NAME
PIN NO.
TYPE
DESCRIPTION
DATA /
6
I/O12t
Serial data input/output, connect to W55FXX. The pin is latched by CLKOUT and ADDR acted as speech data and address respectively. General purpose I/O function. If pin 9 (SPEECH_SEL) is trapped to high at VSB power on, this function will be active. Output clock numbers of this pin decide which mode is selected. Connect to W55FXX. General purpose I/O function. If pin 9 (SPEECH_SEL) is trapped to high at VSB power on, this function will be active. Output mode signal to W55FXX serial Flash. General purpose I/O function. If pin 9 (SPEECH_SEL) is trapped to high at VSB power on, this function will be active. Current type output driving an external speaker. The function is only working in VDD 5V OK. LED output control. This is a multi-function pin with SPEAKER. When the LED_SEL register (Bank0 Index 17h) is set to 1, LED output function will be active. Otherwise, set to 0 (default), this pin serves as SPEAKER output. During VSB 5V power on, this pin is used to trap whether using speech function or GPIO function. Trapping low means using speech function (i.e. pin45-48, pin1, pin4-8 are as speech function). Trapping high means using GPIO function (i.e. pin45-48, pin1, pin4-8 are as GPIO function). The I/O control and status is defined in BANK0 Index 13h~16h. Fan speed control PWM output. When the power of VDD is 0v, this pin will drive logic 0. The power of this pin is supplied by VSB 5V. I2C device address bit0 trapping during 5VSB power on. Fan speed control PWM output. When the power of VDD is 0v, this pin will drive logic 0. The power of this pin is supplied by VSB 5V. I2C device address bit1 trapping during 5VSB power on. Voltage Supply readouts from CPU. After programming, this pin can be VID output to voltage regulator to generate Vcore for CPU.
GPIO2
I/OD12ts
CTRL / GPIO3
7
OUT12 I/OD12ts
MODE / GPIO4
8
OUT12 I/OD12ts
SPEAKER LED
9
OUT12 OUT12
SPEECH_SEL
INts
PWMOUT1/
10
OUT12
A0 PWMOUT2 / 11
INts OUT12
A1 VID1 12
INts I/O 1 2 t s
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W83791D/G
PIN DESCRIPTION, continued
PIN NAME
PIN NO.
TYPE
DESCRIPTION
VDD (5V)
13
POWER
+5V VDD power. Bypass with the parallel combination of 10F (electrolytic or tantalum) and 0.1F (ceramic) bypass capacitors. Internally connected to all digital circuitry. CPU presence signal. 0 means CPU is present. 1 means CPU is absent. CASE OPEN detection. An active high input from an external device when case is Intruded. This signal can be latched in external circuit which power is supplied by VBAT, even if W83791D/G is power off. Voltage Supply readouts from CPU. After programming, this pin can be VID output to voltage regulator to generate Vcore for CPU. 0V to +5V amplitude fan tachometer input Serial Bus Clock. Serial Bus bi-directional Data. Fan speed control PWM output. When the power of VDD is 0v, this pin will drive logic 0. The power of this pin is supplied by VSB 5V. VID table selection trapping during RSMRST (0: Intel VRM 8.2/8.3; 1: Intel VRM 9.0). When the trapping pin get a logic 1, the beep warning function is according to Intel VRM 9.0 VID. Voltage Supply readouts from CPU. After programming, this pin can be VID output to voltage regulator to generate Vcore for CPU. Voltage Supply readouts from CPU. After programming, this pin can be VID output to voltage regulator to generate Vcore for CPU. Alarm beep output. Normal, this pin is low. When abnormal event happens, this pin will output alarm frequency. Internally connected to all analog circuitry. The ground reference for all analog inputs. 0V to 4.096V FSR Analog Inputs. This pin is power for W83791D/G. Bypass with the parallel combination of 10F (electrolytic or tantalum) and 0.1F (ceramic) bypass capacitors. This pin is power for W83791D/G.
GNDD SLOTOCC# CASEOPEN
14 15 16
DGROU ND INts I/O6ts
VID4
17
I/O 1 2 t s
FAN3INFAN1IN SCL SDA PWMOUT3 /
18-20 21 22 23
INts INts I/OD8ts OUT12
VID_V90
INts
VID2
24
I/O 1 2 t s
VID3
25
I/O 1 2 t s
BEEP GNDA -5VIN +5VSB
26 27 28 29
OD12 AGROUN D AIN POWER
VBAT
30
POWER
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PIN DESCRIPTION, continued
PIN NAME
PIN NO.
TYPE
DESCRIPTION
-12VIN +12VIN VINR1 +3.3VIN VINR0 VCORE VREF VTIN3 / PIITD3 VTIN2 / PIITD2 VTIN1 / PIITD1 VID0
31 32 33 34 35 36 37 38
AIN AIN AIN AIN AIN AIN AOUT AIN
0V to 4.096V FSR Analog Inputs. 0V to 4.096V FSR Analog Inputs. 0V to 4.096V FSR Analog Inputs. 0V to 4.096V FSR Analog Inputs. 0V to 4.096V FSR Analog Inputs. 0V to 4.096V FSR Analog Inputs. Reference voltage. Thermistor 3 terminal input. (Default) PentiumTM II diode 3 input. This multi-functional pin is programmable.
39
AIN
Thermistor 2 terminal input. (Default) PentiumTM II diode 2 input. This multi-functional pin is programmable.
40
AIN
Thermistor 1 terminal input. (Default) PentiumTM II diode 1 input. This multi-functional pin is programmable.
41
I/O 1 2 t s
Voltage Supply readouts from CPU. After programming, this pin can be VID output to voltage regulator to generate Vcore for CPU. Over temperature Shutdown Output for temperature sensor 1-3. Interrupt request. General purpose I/O function. If pin 9 (SPEECH_SEL) is trapped to high at VSB power on, this function will be active. System Management Interrupt (open drain). LED output control. This is a multi-function pin with SMI. When the register (Bank0 Index 17h bit7 and Index A6h bit 6) is set to 1, LED output function will be active. Otherwise, set to 0 (default), this pin serves as SMI#. Event trapping to selection speech output sound. Default is high edge trigger. General purpose I/O function. If pin 9 (SPEECH_SEL) is trapped to high at VSB power on, this speech function will be active. The I/O control and status is defined in BANK0 Index 13h~14h. Otherwise, GPIO pin can be selected by registers.
OVT# IRQ / GPIO10
42 43
OD12 OUT12 I/OD12ts
SMI# / LED
44
OD12 OUT12
EVNTRP1/ GPIO5
45
I/O12ts
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PIN DESCRIPTION, continued
PIN NAME
PIN NO.
TYPE
DESCRIPTION
EVNTRP2-3/ GPIO6-7/ FANIN4-5
46-47
I/O12ts I/O12ts
Event trapping to selection speech output sound. Default is high edge trigger. General purpose I/O function. If pin 9 (SPEECH_SEL) is trapped to high at VSB power on, this speech function will be active. The I/O control and status is defined in BANK0 Index 13h~14h. Otherwise, GPIO pin or FAN inputs can be selected by registers. Event trapping to selection speech output sound. General purpose I/O function. If pin 9 (SPEECH_SEL) is trapped to high at VSB power on, this function will be active. The I/O control and status is defined in BANK0 Index 13h~14h. Otherwise, GPIO pin or PWMOUT Fan control can be selected by registers, but the PWMOUT can not support Smart Fan.
EVNTRP4/ GPIO8/ PWMOUT4
48
I/O12ts I/O12ts
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6. FUNCTION DESCRIPTION 6.1 General Description
The W83791D/G provides 10 analog positive inputs, 5 fan speed inputs , at most 5 sets for fan PWM (Pulse Width Modulation) control, 3 thermal inputs from remote thermistors, 2N3904 transistors or PentiumTM II/III (Deschutes) thermal diode outputs, case open detection and beep function output when the monitored values exceed preset ranges, including the voltage, temperature, and fan count. Moreover, W83791D/G uniquely provides several innovative and practical functions to make the whole system more efficient and compliant with future trend of network management, such as speech function, ASF sensor compliant, SMBus 2.0 ARP command compatible, VID table selection trapping, 5VID output control, and so forth. Once the monitoring function of W83791D/G is enabled, the watch dog machine will monitor every function and store the values to registers for comparison with preset ranges. If the monitoring value exceeds the limit value, the interrupt status will be set to 1 and W83791D/G will issue interrupt signals such as SMI# and IRQ if not masked..
6.2
Access Interface
The W83791D/G provides I2C Serial Bus for microprocessor to read/write internal registers. In the W83791D/G, there are three serial bus addresses. Through the first address defined at CR [48h], all the registers can be read and written except CPUT1/CPUT2 temperature sensor registers. The read/write of the CPUT1/CPUT2 temperature sensor registers can be implemented through the second address (defined at CR [4Ah] bit2-0) and the third address (defined at CR [4Ah] bit6-4). The first serial bus address of W83791D/G has 2 hardware setting bits set by pin10-11. The address is 001011[pin11], and [pin10]. Hence, the content of CR [48h] would be 00101110 if pin11=1 and pin10=0.
6.2.1 The first serial bus access timing (a) Serial bus writes to internal address register followed by the data byte
0 SCL SDA
Start By Master
7
8
0
7
8
0
1
0
1
1
0
1
R/W
Ack by 791D
D7
D6
D5
D4
D3
D2
D1
D0
Ack by 791D
Frame 1 Serial Bus Address Byte 0
Frame 2 Internal Index Register Byte 7 8
SCL (Continued) SDA (Continued) D7 D6 D5 D4 D3 D2 D1 D0
Ack by 791D 784R Stop by Master
Frame 3 Data Byte
Figure 1. Serial Bus Write to Internal Address Register followed by the Data Byte
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(b) Serial bus read from a register
0 SCL SDA
Start By Master
7
8
0
7
8
0
1
0
1
1
0
1
R/W
Ack by 791D
D7
D6
D5
D4
D3
D2
D1
D0
Ack by 791D
Frame 1 Serial Bus Address Byte 0
Frame 2 Internal Index Register Byte
0
7
8
0
7
8
0
Repeat start by Master
1
0
1
1
0
1
R/W
Ack by 791D
D7
D6
D5
D4
D3
D2
D1
D0
Ack by Master Stop by Master
Frame 3 Serial Bus Address Byte 0
Frame 4 Data Byte
Figure 2. Serial Bus Read from Internal Address Register
6.3
Speech Function
6.3.1 General Description The W83791D/G is a derivative of Winbond's PowerSpeechTM synthesizers. There are up to 5 hardware trigger inputs, 17 Hardware Monitor event and 128 programmable software event trigger inputs. If more than two events happen simultaneously, the priority set by the internal H/W is: SLOTOCC# > EVNTRAP1 > EVNTRAP2 > EVNTRAP3 > EVNTRAP4 > EVNTRAP5 > TRIGREG (Index 09h) 128 events > VIN0 > VIN1> others (VIN2 -VIN9, TEMP, FAN, case open). Software trigger is able to accommodate 128 event triggers, with timeout register (index 08h) enabled in advance for allowance of time on detecting devices. That is, once the system's power is on, BIOS can fill trigger event and speech voice will not be sent till the system fails owing to timeout. In addition, to prevent events from taking place simultaneously. 6.3.2 Event Trigger Queue W83791D/G provides 8 byte FIFO queue to store event trigger, for example, the first 8 event can be served by speech and speech will clear FIFO queue after service. Coding of Speech program must assign correct CPU_MODE event vector to issue correct speech voices correspondent to speech trigger events. For example, CPU_MODE event vector =1 represents absence of CPU, then coding speech with CPU is absent voice. When W83791D/G detects no CPU exists, it will send vector = 1 to speech synthesizer and play this voice data. Following is the block diagram of the 8-Byte event trigger queue.
Enable Timeout CLK 1 HZ
(Index 0Ah, b6)
8-bit Counter Timeout Comparator
TRIG_REG Event Trigger Data
Trigger Timeout Register
(Index 08h)
(Index 09h, b6~0)
8-Byte Event Trigger Queue
Figure 3. Event trigger Queue
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As BIOS usually has POST (Power On Self Test) program, then it will test every item step by step if no failure takes place, however, if it detects a failure on a specific item, it will hang on there. Therefore, BIOS could write timeout value to register 08h and start timer setup speech trigger event (register 09h), then is BIOS test program started. Whenever the system is hang on specific item such as DRAM testing, W83791D would say "DRAM test fails" after the timeout previously set at CR [08h]. On the contrary, if DRAM test is ok, then BIOS could update the timeout value and proceed to the next test program. Below is the speech CPU_MODE table of W83791D/G:
CPU_MODE ITEM DEFINITION VECTOR (H)
POI SLOTOCC EVNTRAP1(TG1) EVNTRAP2 EVNTRAP3 EVNTRAP4 EVNTRAP5 TRIGREG IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 IN9 TEMP1 TEMP2 TEMP3 FAN1 FAN2 FAN3 CHS_EV
Table 1 CPU_MODE
Reserverd CPU present or absent Hardware trgger1 Hardware trgger2 Hardware trgger3 Hardware trgger4 Hardware trgger5 I2C setting software trigger Vcore(VIN0 ) exceed limit VINR0(VIN1) exceed limit (+3.3VIN)VIN2 exceed limit (5VDD)VIN3 exceed limit (+12VIN)VIN4 exceed limit (-12VIN)VIN5 exceed limit (-5VIN)VIN6 exceed limit VSB(VIN7) exceed limit VBAT(VIN8 ) exceed limit (VINR1)VIN9 exceed limit VTIN1 exceed limit VTIN2 exceed limit VTIN3 exceed limit FAN1 count over limit FAN2 count over limit FAN3 count over limit Case open trigger
0,32 1 2 3 4 5 6 80-FF 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50
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6.3.3 Connection of EEPROM As described previously the W83791D/G has connectable W55FXX to store voice data. To expand the storage capacity, users can select many W55FXX to connect with each other. The maximum capacity could be up to 16Mbit. Following is the connection chart of W55FX with W83791D/G.
EEPROM
DATA ADDR CLK CTRL MODE EOP
EEPROM
DATA ADDR CLK CTRL MODE EOP
SLOTOCC# EVTTRAP 1: 5
DATA ADDR CLK CTRL MODE EOP
Speech Synthesizer (W83791D)
9-bit DAC
SPK/LED
Internal programmable trigger
Hardware monitor status trigger
Figure 4 Speech Function Diagram
6.3.4 Speaker Output Speech output pin is a 8 bit Current D/A converter, with which loading is needed. The resistor could range from 510~1K ohm and bipolar could be a low power NPN bipolar with of 120 - 160. Usually, an 8050D transistor is appropriate. The spec of speaker is 8 . Besides, SPK can also connect to AC97 codec chip Line_Out. C is decouple capacitor and is usually 200p- 0.01uF
8 ohm speaker SPK R C 8050D, NPN transistor
Figure. 5
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6.4 Address Resolution Protocol (ARP) Introduction
As the W8791D/G is a slave device existing on the System Management Bus, it must have a unique address to prevent itself from conflicting with the other devices existing on the same bus. In order to solve the problem of address conflicts, SMBus version 2.0 introduces the concept of dynamically assigned address called Address Resolution Protocol (ARP). By such mechanism, each device existing on the SMBus will be given a unique slave address if it is a ARP-capable device. Thus, to meet the new spec, W83791D/G uniquely provides ARP compliant function to acquire a unique slave address. The typical process of ARP contains several steps, including Prepare to ARP, Reset Device, Get UDID, Assign Address, and so on. Whenever the slave device accepts the command of ARP master, it must reply an Acknowledgement to the ARP master, thus the ARP master is able to carry on the next step. In order to provide a mechanism to isolate device for the purpose of address assignment, each device must implement a unique device identifier (UDID). The UDID is a 128-bit number comprised of several field, including Device Capabilities, Version Revision, Vendor ID, Device ID, Interface, Subsystem Vendor ID, Subsystem Device ID, and Vendor Specific ID. After the UDID of the device is sent to the ARP master, the ARP master will then assign a random address not in the Used Address Pool to the device Generally speaking, there are eleven possible commands to read /write the data of SMBus device, and a slave device may use any or all of the eleven protocols to communicate. These protocols are Quick Command, Send Byte, Receive Byte, Write Byte, Write Word, Read Byte, Read word, Process Call, Block Write, and Block Write-Block Read Process Call. W83791D/G itself supports the Block Write-Block Read Process with PEC to communicate with ARP Master. Following is a description of the SMBus packet protocol diagrams element key. Not all protocol elements will be present in every command, that is, not all packets are required to include the Packet Error Code. 1-bit S 7 Slave Address S Sr Rd Wr A 1 1 Wr A 8 Command 1 A 8 PEC 1 A 1-bit P
Start Condition Repeated Start Condition Read (bit value of 1) Write (bit value of 0) Acknowledge (this bit position may be `0' for an ACK or `1' for a NACK)
P PEC
Stop Condition Packet Error Code Master-to-Slave Slave-to-Master
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Relative command list:
SLAVE ADDRESS COMMAND DESCRIPTION
C2h C2h C2h C2h C2h C2h C2h
01h 02h 03h 04h
Prepare to ARP Reset device (general) Get UDID (general) Assign address
Slave_Addr | 1 Direct Get UDID Slave_Addr | 0 Direct Reset 05h-1Fh Reserved.
Following is an example of the Block Write-Block Read Process Call. The Block Write-Block Read Process Call is a two-part message. It begins with a salve address and a write condition. After the command code the host issues a write count M that describes how many more bytes will be written in the first part of the message. The second part of the message is a block of read data beginning with a repeated start condition followed by thee salve address and a Read Bit. The next read byte count N indicates how many more data will be read in the second part of the message. Note that the combined data payload must not exceed 32bytes. Besides, W83791D/G also provides packet error code (PEC) to insure the accuracy during data transmission. 1 S 7 Slave Address 1 Wr 1 A 8 1 8 Byte Count=M 1 A 8 Data Byte 1 1 A ...
Command Code A
8 Data Byte 2
1 A
... ...
8 Data Byte M
1 A ...
1 Sr
7
1
1
8
1
8
1
1 ...
Slave Address Rd A
Byte Count=N A
Data Byte 1 A
8
1
... ...
8
1
8
1
1 P
Data Byte 2 A
Data Byte N A
PEC A
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6.5 ASF (Alert Standard Format) Introduction
In order to implement network management in OS-absent, W83791D/G provides ASF Response Registers to meet ASF sensor spec. As a result, the network server is able to monitor several environmental status of the client in OS-absent by PET frame values returned from W83791D/G, including temperature, voltage, fan speed, and case open. In below is the ASF diagram: Alert Message LAN on Card
Management Server
Polling PCI Bus LAN on Board SMBus Chipset
(PET Subset) Motherboard
791D Slave
Figure 6. ASF Block Diagram
6.5.1 Platform Event Trap (PET) PET is the ASF transmit protocol used to provide common fields for trap regardless of trap source. The variable bindings fields in a PET frame contain the system and sensor information for an event, such as event sensor type, event type, event offset, event source type, sensor device, sensor number, entity ID, entity instance, event status index, event status, and event severity. Each field has its definition and is described in the following table.
PET VARIABLE BINDING FIELD DESCRIPTION
Event Sensor Type
The Event Sensor Type field indicates what types of events the sensor is monitoring. E.g. temperature, voltage, fan, etc. The Event Type indicates what type of transition/state change triggered the trap. The Event Offset indicates which particular event occurred for a given Even Type. The Event Source Type describes the originator of the event. It is ASF1.0 (68h) for all PET frames defined by this specification.
Event Type Event Offset Event source Type
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Platform Event Trap (PET), continued.
PET VARIABLE BINDING FIELD
DESCRIPTION
Sensor Device Sensor Number Entity ID Entity Instance Event Status Index
The Sensor Device is the SMBus address of the sensor that caused the event for the PET frame. The Sensor Number is used to identify a given instance of a sensor relative to the Sensor Device. The Entity ID indicates the platform entity the event is associated with. E.g. processor, system board, etc. The Entity Instance indicates which instance of the Entity the event is for. E.g. processor 1 or processor 2. The Event Status Index identifies a unique event monitored by the ASF-sensor. It is zero-based, sequential, continuous, and ranging form 0-37h. The Event Status indicates the event state of the ASFsensor device associated with the message's Event Status Index. The Event Severity gives the management station an indication of the severity of the event in the PET frame. Typical values are Monitor (0x01), Non Critical (0x08), or Critical Condition (0x10).
Event Status
Event Severity
Following is the illustration of ASF SMBus command for Get Event Data. 1 S 7 Slave Address ASF-sensor Address 8 Wr Data 1 1 A 1 Wr 0 1 A 0 8 Command Sensor Device 0000 0001 1 Data A 0 8 Wr Data 3 Event Index 00ii iiii 1 A 0 8 0000 0100 1 ... 0
Wr Byte Count A
8 Wr 2
1 A Status 0
8 Wr Data 4 Reserved 0000 0000
1 A 0 ...
Sub Command 0 Get Event Data 0001 0001
Version Number 0001 0000 1 R 1
1 Sr
7 Slave Address ASF-sensor Address
1 A 0
8 Rd Byte Count 0000 1010 to 0000 1111
1 A 0 ...
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1 A 0 8 Rd Data 4 8 Rd Data 1 Status 1 A 8 Rd Data 5 1 A 0 8 Rd Data 2 1 A 8 Rd Data 3 Event Type 1 A 8 Rd Data 7 Sensor Device 1 A 0 1 A 0 ... ...
Event Sensor Type 0 1 A 8 Rd Data 6
Event Offset 0
Event Source 0 Type 1 A 0 8
Event Severity 0
8 Rd Data 8 Sensor Number
1 A 0
8 Rd Data 10 Entity Instance
1 A 0 ...
Rd Data 9 Entity
8 ... PEC From zero to five bytes of Event Data [data dependent]
1 A 1
1 P
6.6
Analog Inputs
The maximum input voltage of the analog pin is 4.096V because the 8-bit ADC has a 16mv LSB. Actually, the application of the PC monitoring would most often be connected to power supply. The CPU V-core voltage, +3.3V and battery voltage can directly connect to these analog inputs. The - 5V, -12V and +12V inputs should be reduced a factor with external resistors to meet the input range. As Figure 7 shows.
+1.8Vcore Positive Inputs +1.5VINR0 +3.3VIN VINR1 V1 Positive Input R1 VBAT 12VIN 5VSB R2 Pin 36 Pin 35 Pin 34 Pin 33 Pin 30 Pin 32 Pin 29 8-bit ADC with 16mV LSB
Negative Input
V3 V4 R7
R5
N12VIN N5VIN
Pin 31 Pin 28
R8 R 10K, 1% VREF VTIN3 Typical Thermister Connection RTHM 10K, 25 C VTIN2 VTIN1 Pin 38 Pin 39 Pin 40
R6 Pin 37
**The Connections of VTIN1 and VTIN2 are same as VTIN3
Figure 7.
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6.6.1 Monitor over 4.096V voltage: The input voltage +12VIN can be expressed as the following equation.
12VIN = V1 x
R2 R1 + R2
The value of R1 and R2 can be selected to 28K Ohms and 10K Ohms, respectively, when the input voltage V1 is 12V. The node voltage of +12VIN should be subject to under 4.096V for the maximum input range of the 8-bit ADC. The pin 13 and pin 29 are discretely connected to the power supply +5V and 5VSB. There are two functions in these pins with 5V. The first function is to supply internal analog power in the W83791D/G and the second one is that these voltages are all connected to internal serial resistors to monitor the +5V and 5VSB voltage.
6.6.2 Monitor negative voltage: The negative voltage should be connected to two series resistors and a positive voltage VREF (equal to 3.6V). In the Figure 11, the voltage V3 and V4 are two negative voltages and are -12V and -5V respectively. The voltage V3 is connected to two serial resistors as well as another positive terminal VREF. Therefore, the voltage node N12VIN would be a positive voltage if the scale of the two serial resistors are carefully selected. It is recommended from Winbond that the scale of the two serial resistors are R5=232K ohms and R6=56K ohm. The input voltage of node -12VIN can be calculated by the following equation.
N12VIN = (VREF + V5 ) x (
where VREF is equal to 3.6V.
232 K ) + V5 232 K + 56 K
If the V5 is equal to -12V then the voltage is equal to 0.567V and the converted hexdecimal data is set to 35h by the 8-bit ADC with 16mV-LSB.This monitored value should be converted to the real negative voltage and the express equation is shown as follows.
V5 =
Where
N12VIN - VREF x 1-
is 232K/(232K+56K). If the N2VIN is 0.567 then the V5 is approximately equal to -12V.
The other negative voltage input V6 (approximate -5V) can also be evaluated by the similar method and the serial resistors can be R7=120K ohms and R8=56K ohms by the Winbond recommended. The expression equation of V6 With -5V voltage is shown as follows.
V6 =
N 5VIN - VREF x 1-
Where the is set to 120K/ (120K+56K). If the monitored ADC value in the N5VIN channel is 0.8635, VREF=3.6V and the parameter is 0.6818, then the negative voltage of V6 can be evaluated -5V.
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6.7 FAN Speed Count and FAN Speed Control
6.7.1 Fan speed count W83791D/G support 5 sets of fan counting. Fan inputs are provided for signals from fans equipped with tachometer outputs. The level of these signals should be set to TTL level, and the maximum input voltage should not be over +5.5V. If the input signals from the tachometer outputs are over the VCC, the external trimming circuit should be added to reduce the voltage to meet the input specification. The normal circuit and trimming circuits are shown as Figure 8.
Determine the fan counter according to:
Count =
1.35 x 10 6 RPM x Divisor 1.35 x 10 6 Count x Divisor
In other words, if the fan speed counter has been read from register CR [28] or CR [29] or CR [2A] or CR [BA] or CR [BB] , then the fan speed can be evaluated by the following equation.
RPM =
The default divisor is 2 and defined at CR47.bit7~4, CR4B.bit7~6, and Bank0 CR5D.bit5~7 which are three bits for divisor. This provides very low speed fan counter such as power supply fan. The followed table is an example for the relation of divisor, RPM, and count.
DIVISOR NOMINAL RPM TIME PER REVOLUTION COUNTS 70% RPM TIME FOR 70%
1 2 (default) 4 8 16 32 64 128
8800 4400 2200 1100 550 275 137 68
6.82 ms 13.64 ms 27.27 ms 54.54 ms 109.08 ms 218.16 ms 436.32 ms 872.64 ms
Table 2
153 153 153 153 153 153 153 153
6160 3080 1540 770 385 192 96 48
9.74 ms 19.48 ms 38.96 ms 77.92 ms 155.84 ms 311.68 ms 623.36 ms 1246.72 ms
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+12V +5V Pull-up resister 4.7K Ohms +12V Pull-up resister 4.7K Ohms
+12V FAN Out GND Fan Input Pin 18/19/20
+12V FAN Out GND
14K~39K
Fan Input
Pin 18/19/20
FAN Connector
W83791D
FAN Connector
10K
W83791D
Figure 8-1. Fan with Tach Pull-Up to +5V
Figure 8-2. Fan with Tach Pull-Up to +12V, or Totem-Pole Output and Register Attenuator
+12V
+12V
Pull-up resister > 1K +12V FAN Out GND Fan Input Pin 18/19/20 +12V FAN Out GND
Pull-up resister < 1K or totem-pole output > 1K
Fan Input
Pin 18/19/20
3.9V Zener
FAN Connector
W83791D
3.9V Zener
FAN Connector Figure 8-4. Fan with Tach Pull-Up to +12V, or Totem-Pole Putput and Zener Clamp
W83791D
Figure 8-3. Fan with Tach Pull-Up to +12V and Zener Clamp
6.7.2 Fan speed control The W83791D/G provides five sets of PWM for fan speed control. The duty cycle of PWM can be programmed by a 8-bit registers defined in the Bank0 CR [81], CR [83], CR [94], CR [9E] and CR [9F]. The default duty cycle is set to 100%, that is, the default 8-bit register is set to 0xFFh. The expression of duty cycle can be represented as follows.
Duty - cycle(%) =
Programmed 8 - bit Register Value x 100% 255
+12V
R1 R2 G D NMOS S + PNP Transistor
PWM Clock Input
C
FAN
Figure 9.
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W83791D/G
6.7.3 Smart Fan Control W83791D/G supports three Smart Fan function and mapping to temp1 (FAN1, PWMOUT1), temp2 (FAN2, PWMOUT2), temp3 (FAN3, PWMOUT3) .Smart Fan Control provides two mechanisms. One is Thermal Cruise mode and the other is Fan Speed Cruise mode.
6.7.3.1. Thermal Cruise mode At this mode, W83791D/G provides the Smart Fan system to automatically control fan speed to keep the temperatures of CPU and the system within specific range. At first a wanted temperature and interval must be set (ex. 55 C 3 C) by BIOS and the fan speed will be lowered as long as the current temperature remains below the setting value. Once the temperature exceeds the high limit (58C), the fan will be turned on with a specific speed set by BIOS (ex: 80% duty cycle) and automatically controlled its PWM duty cycle with the temperature varying. Three conditions may occur: (1) If the temperature still exceeds the high limit (ex: 58C), PWM duty cycle will increase slowly. If the fan has been operating in its full speed but the temperature still exceeds the high limit (ex: 58C), a warning message will be issued to protect the system. (2) If the temperature goes below the high limit (ex: 58C), but still above the low limit (ex: 52C), the fan speed will be fixed at the current speed because the temperature is in the target range (ex: 52 C ~ 58C). (3) If the temperature goes below the low limit (ex: 52C), PWM duty cycle will decrease slowly to 0 or a preset stop value until the temperature exceeds the low limit. Figure 10-1, 10-2 gives an illustration of Thermal Cruise Mode.
A 58C 55C 52C 100 50 0
Figure 10-1
Fan Start = 20%
B
C
D
PWM Duty Cycle
A 58C 55C 52C 100 50 0
B
C
D
PWM Duty Cycle
Fan Start = 20%
Fan Stop = 10%
Fan Start = 20%
Figure 10-2
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6.7.3.2. Fan Speed Cruise mode At this mode, W83791D/G provides the Smart Fan system to automatically control the fan speed within a specific range. In the beginning, a wanted fan speed count and interval must be set (ex. 160 10) by BIOS. As long as the fan speed count remains in the specific range, PWM duty cycle will keep the current value. If current fan speed count is higher than the high limit (ex. 160+10), PWM duty cycle will be increased to make the count under the high limit. On the other hand, if current fan speed count is less than the low limit (ex. 160-10), PWM duty cycle will be decreased to make the count higher than the low limit. See Figure 10-3 example.
Count 170 160 150 100 50 0
Figure 10-3
A
C
PWM Duty Cycle
Of course, Smart Fan control system can be disabled and the fan speed control algorithm can be programmed by BIOS or application software.
6.8
Temperature Measurement Machine
The temperature data format is 8-bit two-complement for sensor 1 and 9-bit two-complement for sensor 2/3. The 8-bit temperature data can be obtained by reading the CR [27h]. The 9-bit temperature data can be obtained by reading the 8 MSBs from the bank0 CR [C0/ C8h] and the LSB from the bank0 CR [C1/C9h] bit 7. The format of the temperature data is show in Table 3.
TEMPERATURE 8-BIT DIGITAL OUTPUT 9-BIT DIGITAL OUTPUT
8-Bit Binary +125C +25C +1C +0.5C +0C -0.5C -1C -25C -55C 0111,1101 0001,1001 0000,0001 0000,0000 1111,1111 1110,0111 1100,1001
8-Bit Hex 7Dh 19h 01h 00h FFh E7h C9h
9-Bit Binary 0,1111,1010 0,0011,0010 0,0000,0010 0,0000,0001 0,0000,0000 1,1111,1111 1,1111,1110 1,1100,1110 1,1001,0010
9-Bit Hex 0FAh 032h 002h 001h 000h 1FFh 1FFh 1CEh 192h
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Table 3
6.8.1 Monitor temperature from thermistor: The W83791D/G can connect three thermistors to measure three different environmental temperatures. The specification of thermistor should be considered to (1) value is 3435K, (2) resistor value is 10K ohms at 25C. In the Figure 11, the themistor is connected by a serial resistor with 10K Ohms (1% error), then connect to VREF (Pin 37). 6.8.2 Monitor temperature from Pentium IITM thermal diode or bipolar transistor 2N3904 The W83791D/G can alternate the thermistor to Pentium II/IIITM thermal diode interface or transistor 2N3904 and the circuit connection is shown as Figure 11. The pin of Pentium II/IIITM D- is connected to power supply ground (GND) and the pin D+ is connected to pin PIITDx in the W83791D/G. The resistor R=30K ohms should be connected to VREF to supply the diode bias current and the bypass capacitor C=3300pF should be added to filter the high frequency noise. The transistor 2N3904 should be connected to a form with a diode, that is, the Base (B) and Collector (C) in the 2N3904 should be tied together to act as a thermal diode.
V R EF R =30K, 1%
Bipolar T ransisto r T emperature S ensor
P IIT D x C =330 0pF
B
C 2N 39 04 E R =3 0K, 1%
W 83791D
OR
P e ntium II/III CPU
T h erminal D iode
D+ C =3300pF D-
P IIT D x
Figure 11.
6.8.3 SMI# interrupt for W83791D Voltage SMI# interrupt for voltage is Two-Times Interrupt Mode. Voltage exceeding high limit or going below low limit will causes an interrupt if the previous interrupt has been reset by reading all the interrupt Status Register. (Figure 12-1)
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6.8.4 SMI# interrupt for W83791D Fan SMI# interrupt for fan is Two-Times Interrupt Mode. Fan count exceeding the limit, or exceeding and then going below the limit (set at value ram index 3Bh and 3Ch), will causes an interrupt if the previous interrupt has been reset by reading all the interrupt Status Register. (Figure 12-2)
High limit
Low limit
Fan Count limit
SMI#
*
*
*
*
SMI#
*
*
*Interrupt Reset when Interrupt Status Registers are read
Figure 12-1. Voltage SMI# Mode
Figure 12-2. Fan SMI# Mode
6.8.5 SMI# interrupt for W83791D/G temperature sensor 1/2/3 (1) Comparator Interrupt Mode Temperature exceeding TO causes an interrupt and this interrupt will be reset by reading all the Interrupt Status Register. Once an interrupt event has occurred by exceeding TO, then reset, if the temperature remains above the THYST, the interrupt will occur again when the next conversion has completed. If an interrupt event has occurred by exceeding TO but has not been reset, the interrupts will not occur again. The interrupts will continue to occur in this manner until the temperature goes below THYST. (Figure 12-3)
(2) Two-Times Interrupt Mode Temperature exceeding TO causes an interrupt and then temperature going below THYST will also cause an interrupt if the previous interrupt has been reset by reading all the interrupt Status Register. Once an interrupt event has occurred by exceeding TO, then reset, if the temperature remains above the THYST, the interrupt will not occur. (Figure 12-4) (3) One-Time interrupt mode Temperature exceeding TO causes an interrupt and then temperature going below THYST will not cause an interrupt. Once an interrupt event has occurred by exceeding TO, then going below THYST, an interrupt will not occur again until the temperature exceeding TO. (Figure 12-5)
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T OI
T OI
T HYST
T HYST
SMI#
*
*
*
*
*
SMI#
*
*
*
*Interrupt Reset when Interrupt Status Registers are read
Figure 12-3. Comparator Interrupt Mode
Figure 12-4. Two-Times Interrupt Mode
T OI
T HYST
SMI#
*
*
*Interrupt Reset when Interrupt Status Registers are read
Figure 12-5. One-Time Interrupt Mode
Note. The IRQ interrupt action like SMI#, but the IRQ is level signal.
6.8.6 Over-Temperature (OVT#) for W83791D/G temperature sensor 1/2/3 (1) Comparator Mode: Temperature exceeding TO causes the OVT# output activated until the temperature is less than THYST. (Figure 13)
(2) Interrupt Mode: Temperature exceeding TO causes the OVT# output activated indefinitely until reset by reading temperature sensor 1 or sensor 2 or sensor 3 registers. Temperature exceeding TO, then OVT# reset, and then temperature going below THYST will also cause the OVT# activated indefinitely until reset by reading temperature sensor 1 or sensor 2 or sensor 3 registers. Once the OVT# is activated by exceeding TO, then reset, if the temperature remains above THYST, the OVT# will not be activated again. ( Figure 13) (3) ACPI Mode At this mode, temperature exceeding one level of temperature separation, starting from 0 degree, causes the OVT# output activated. OVT# will be activated again once temperature exceeds the next level. OVT# output will act the same manner when temperature goes down. (Figure 13-1)
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The granularity of temperature separation between each OVT# output signal can be programmed at Bank0 CR [4Ch] bit 4-5.
To
T HYST
OVT#
(Comparator Mode; default)
OVT#
(Interrupt Mode)
*
*
*
*Interrupt Reset when Temperature 1/2/3 is read
Figure 13 Over-Temperature Response Diagram
('C) 100 90 80 70 60 50 40 30 20 10 0 OVT#
Current Temperature
Figure 13-1. ACPI Mode
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7. CONTROL AND STATUS REGISTER 7.1 Speech Flash Memory Address Registers Index 00h-02h (Bank 0)
Power on default: 00h
INDEX NAME ATTRIBUTE DESCRIPTION
00h 01h 02h
SPEECHA 0 SPEECHA 1 SPEECHA 2
R/W R/W R/W
Speech Flash Address 0. Set speech flash programming address bits [7:0]. Speech Flash Address 1. Set speech flash programming address bits [15:8]. Speech Flash Address 2. Set speech flash programming address bits [23:16].
7.2
Speech Flash Memory Data Registers Index 03h-06h (Bank 0)
NAME ATTRIBUTE DESCRIPTION
Power on default: 00h
INDEX
03h 04h 05h 06h
SPEECHD0 SPEECHD1 SPEECHD2 SPEECHD3
R/W R/W R/W R/W
Speech Flash Data data bits [7:0]. Speech Flash Data data bits [15:8]. Speech Flash Data data bits [23:16]. Speech Flash Data data bits [31:24].
0. Set speech flash programming 1. Set speech flash programming 2. Set speech flash programming 3. Set speech flash programming
7.3
BIT
Speech Flash Memory Control Register Index 07h (Bank 0)
NAME ATTRIBUTE DESCRIPTION
Power on default: 00h 7 PROG_ACTIVE R/W Program Active Command. If set this bit to 1, the serial flash will be active according the Flash Program Mode. Reading this bit, the bit will return a Serial Flash Busy (SER_BUSY). And this is pulse, if read this bit show "0" Reserved. Flash Program Mode FLASHCTRL[3:0] 0000b No action 0001b Program mode 0010b Erase all 0011b Page code 0100b Erase 4K bytes 0101b Erase 16K bytes 0110b Page code read out 0111b Read flash data
6:4 3:0
Reserved PROGMODE R/W
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Program procedure: 1. Set Flash address (3-bytes) 2. Set Flash Data (4-bytes) 3. Set Flash control "Program mode" 4. Set program command active (PROG_ACTIVE) Erase 4K: 1. Set Flash Address (must be 4K address boundary) 2. Set Flash control register
7.4
BIT
Event Trigger Timeout Register Index 08h (Bank 0)
NAME ATTRIBUTE DESCRIPTION
Power on default: 00h 7:0 TRIG_TIME R/W Event Trigger Timeout Timer Setting. When software or firmware write trigger event, that don't write to speech queue until this register is timeout. This unit is Second. Default is 00, that is, the software event doesn't need to wait then write to sound event queue. Note that, this function is controlled by Speech Input Property (Index 0Ah).
7.5
BIT
Speech Programmable Trigger Register Index 09h (Bank 0)
NAME ATTRIBUTE DESCRIPTION
Power on default: 80h 7 TR_RDY RO Programmable Trigger Register Ready. If return to 1, the software or firmware can write next event to trigger register. If return to 0, the software or firmware cannot write trigger event to event queue, that is, the timer is not timeout yet. Speech Programmable Trigger Register. The software or firmware can set these bits to trigger speech sound. The vectors of sound trigger are shown as follows. If the bit of trigger register ready is logic 0, this trigger register will be ignored. Therefore, the bit of the trigger ready should be read before programming this register. TRIG_REG<6:0> Speech Sound Vector 00h Vector 80h (1000_0000b) (=80h+00h) 01h Vector 81h (1000_0001b) (=80h+01h) 02h Vector 82h (1000_0010b) (=80h+02h) : : Vector (80h+n) N : : 7Eh Vector FEh (1111_1110b) (=80h+7Eh) 7Fh Vector FFh (1111_1111b) (=80h+7Fh)
6:0
TRIG_REG
R/W
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7.6
BIT
Speech Input Trigger Property Register Index 0Ah (Bank 0)
NAME ATTRIBUTE DESCRIPTION
Power on default: 00h 7 6 5 4:0 En_Program En_Timeout Busy EVNTRAP51 Polarity R/W WO RO R/W Enable W83791D to program external serial flash memory and change GPIO pin to Speech mode pin. Enable Software/Firmware Trigger Timeout Function. This bit sets the Event Trigger Timeout Function in Index 08h. If read this bit return "1" means SPKOUT is in busy. Write `0' the EVNTRAP5-1 will positive edge trigger. Write `1' will negative edge trigger.Default is `0'.
7.7 7.8
BIT
Reserved Register Index 0Bh (Bank 0) VID and VCORE voltage Property Register Index 0Ch (Bank 0)
NAME ATTRIBUTE DESCRIPTION
Power on default: 00h 7:1 0 Reserved VRM_check Reserved. Read only If read 1, the power on VCORE checking will be according to Intel VRM9.x . This bit is powered VSB.
7.9
Speech Flash Memory Read Data Registers Index 0Dh-0Eh (Bank 0)
NAME ATTRIBUTE DESCRIPTION
Power on default: 00h
INDEX
0Dh 0Eh
SPEECHRD0 SPEECHRD1
RO RO
Speech Flash Read Data 0. data bits [7:0]. Speech Flash Read Data 1. data bits [15:8].
Speech flash reading Speech flash reading
7.10
Reserved Register Index 0Fh (Bank 0)
7.11 VID Control/Status Register Index 10h (Bank 0)
Power on default: 00h
BIT NAME ATTRIBUTE DESCRIPTION
7 6:5 4:0
EN_VIDOUT Reserved VID_DATA
R/W R/W
Enable VID Output. Reserved. VID Output Data. Read this register will return programmed data of VID_DATA.
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7.12 Entry Disable VID Output Control Register Index 11h (Bank 0)
Power on default: 00h
BIT NAME ATTRIBUTE DESCRIPTION
7:0
Entry_Dis
Write
Entry Disable VID Output Control. When write a serial pattern: 5Ah, 73h, B2h, E0h, the VID output control will enable. If write a serial pattern: A5h, 4Ch, D9h, 8Ah, the VID output control will disable.
7.13 VID Output Tolerance/Limit Register Index 12h (Bank 0)
Power on default: 60h
BIT NAME ATTRIBUTE DESCRIPTION
7:5 4:0
VID_limit VID_PIN
R/W Read Only
VID +/- Tolerance/Limit. Default is 3. VID Pin Data Reading.
7.14 GPIO Control Register I Index 13h (Bank 0)
Power on default: 00h
BIT NAME ATTRIBUTE DESCRIPTION
7 6 5 4 3 2 1 0
GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
R/W R/W R/W R/W R/W R/W R/W R/W
GPIO7 Control Bit. Set to 1, GPIO7 serves GPIO7 serves as input. Default is input. GPIO6 Control Bit. Set to 1, GPIO6 serves GPIO6 serves as input. Default is input. GPIO5 Control Bit. Set to 1, GPIO5 serves GPIO5 serves as input. Default is input. GPIO4 Control Bit. Set to 1, GPIO4 serves GPIO4 serves as input. Default is input. GPIO3 Control Bit. Set to 1, GPIO3 serves GPIO3 serves as input. Default is input. GPIO2 Control Bit. Set to 1, GPIO2 serves GPIO2 serves as input. Default is input. GPIO1 Control Bit. Set to 1, GPIO1 serves GPIO1 serves as input. Default is input. GPIO0 Control Bit. Set to 1, GPIO0 serves GPIO0 serves as input. Default is input.
as output. Set to 0, as output. Set to 0, as output. Set to 0, as output. Set to 0, as output. Set to 0, as output. Set to 0, as output. Set to 0, as output. Set to 0,
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7.15 GPIO Data/Status Register I Index 14h (Bank 0)
Power on default: 00h
BIT NAME ATTRIBUTE DESCRIPTION
7
GPIO7
R/W
GPIO7 Data/Status Register. Write this bit, the data will response to GPIO7, set to output mode. If read this register, will return this pin data that can input or output in this pin. GPIO6 Data/Status Register. Write this bit, the data will response to GPIO6, set to output mode. If read this register, will return this pin data that can input or output in this pin. GPIO5 Data/Status Register. Write this bit, the data will response to GPIO5, set to output mode. If read this register, will return this pin data that can input or output in this pin. GPIO4 Data/Status Register. Write this bit, the data will response to GPIO4, set to output mode. If read this register, will return this pin data that can input or output in this pin. GPIO3 Data/Status Register. Write this bit, the data will response to GPIO3, set to output mode. If read this register, will return this pin data that can input or output in this pin. GPIO2 Data/Status Register. Write this bit, the data will response to GPIO2, set to output mode. If read this register, will return this pin data that can input or output in this pin. GPIO1 Data/Status Register. Write this bit, the data will response to GPIO1, set to output mode. If read this register, will return this pin data that can input or output in this pin. GPIO0 Data/Status Register. Write this bit, the data will response to GPIO0, set to output mode. If read this register, will return this pin data that can input or output in this pin.
6
GPIO6
R/W
5
GPIO5
R/W
4
GPIO4
R/W
3
GPIO3
R/W
2
GPIO2
R/W
1
GPIO1
R/W
0
GPIO0
R/W
7.16 GPIO Control Register II Index 15h (Bank 0)
Power on default: 10h
BIT NAME
EN_GPIO10
ATTRIBUTE
DESCRIPTION
7 6 5
R/W
Set to 1, pin 43 will serve as a general purpose I/O, GPIO10 is stand along with other GPIO pin. Reserved. Write `1' means programmed VID output value as you wish. Default is `0'. Note: Programmed VID must be carefully, it may cause CPU damaged. Set to 0, FAN4/5, PWM4/5 pin switch to GPIO6-GPIO9. Set to 1 is FAN4/5 and PWM4/5. Default is 1.
Reserved
VID_Protect
R/W
4
SEL_GPIO
R/W
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GPIO Control Register II Index 15h (Bank 0) , continued .
BIT
NAME
ATTRIBUTE
DESCRIPTION
3 2 1 0
GPIO11 GPIO10 GPIO9 GPIO8
R/W R/W R/W R/W
GPIO11 Output Control Bit. Set to 1, GPIO11 serves as output. Set to 0, GPIO11 serves as input. Default is input. GPIO10 Output Control Bit. Set to 1, GPIO10 serves as output. Set to 0, GPIO10 serves as input. Default is input. GPIO9 Output Control Bit. Set to 1, GPIO9 serves as output. Set to 0, GPIO9 serves as input. Default is input. GPIO8 Output Control Bit. Set to 1, GPIO8 serves as output. Set to 0, GPIO8 serves as input. Default is input.
7.17 GPIO Output Data and Status Register II Index 16h (Bank 0)
Power on default: 00h
BIT NAME ATTRIBUTE DESCRIPTION
7:4 3
Reserve d GPIO11 R/W
Reserved. GPIO11 Data/Status Register. Write this bit, the data will response to GPIO11, set to output mode. If read this register, will return this pin data that can input or output in this pin. GPIO10 Data/Status Register. Write this bit, the data will response to GPIO10, set to output mode. If read this register, will return this pin data that can input or output in this pin. GPIO9 Data/Status Register. Write this bit, the data will response to GPIO9, set to output mode. If read this register, will return this pin data that can input or output in this pin. GPIO8 Data/Status Register. Write this bit, the data will response to GPIO8, set to output mode. If read this register, will return this pin data that can input or output in this pin.
2
GPIO10
R/W
1
GPIO9
R/W
0
GPIO8
R/W
7.18 LED Control Register Index 17h (Bank 0)
Power on default: 00h
BIT NAME ATTRIBUTE DESCRIPTION
7 6:3
LED_SEL Reserved
R/W
This bit sets to 1, the LED function will be active on the pin 9 (SPEAKER/LED). Set to 0 (default), select SPEAKER output function. Reserved.
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LED Control Register Index 17h (Bank 0) , continued.
BIT
NAME
ATTRIBUTE
DESCRIPTION
2:0
LED_CLK
R/W
LED Flashed Time Control. LED_CLK Description 000b LED off. Always drive logical low in LED pin. (Default) 001b 4 Hz, 4 times for 1 second. 010b 2 Hz, 2 times for 1 second. 011b 1 Hz, 1 times for 1 second. 100b 1/2 Hz, 1 time for 2 seconds. 101b 1/4 Hz, 1 time for 4 seconds. 110b 1/8 Hz, 1 time for 8 seconds. 111b LED on. Always drive logical high in LED pin if LED function is active.
7.19 User Defined Registers Index 18h-1Ch (Bank 0)
User defined registers. Write a data to the mapped register will return a prior written data when read this mapped register.
7.20 Speech Control Register 1 Index 1Dh (Bank 0)
Power on default: 00h
BIT NAME ATTRIBUTE DESCRIPTION
7
EN_FAN2_SPK
R/W
6
EN_FAN1_SPK
R/W
5
EN_T2_SPK
R/W
4
EN_T1_SPK
R/W
3
EN_V5_SPK
R/W
2
EN_V33_SPK
R/W
1
EN_T3_SPK
R/W
0
EN_V25A_SPK
R/W
Enable SPEECH output from FAN 2 if the monitor value exceeds the limit value. Write 1, enable SPEECH output. Default 0. Enable SPEECH output from FAN 1 if the monitor value exceeds the limit value. Write 1, enable SPEECH output. Default 0. Enable SPEECH output from Temperature Sensor 2 if the monitor value exceeds the limit value. Write 1, enable SPEECH output. Default 0. Enable SPEECH output from Temperature Sensor 1 if the monitor value exceeds the limit value. Write 1, enable SPEECH output. Default 0. Enable SPEECH output from VDD (5V) if the monitor value exceeds the limit value. Write 1, enable SPEECH output. Default 0. Enable SPEECH output from 3.3V if the monitor value exceeds the limit value. Write 1, enable SPEECH output. Default 0. Enable SPEECH output from Temperature Sensor 3 if the monitor value exceeds the limit value. Write 1, enable SPEECH output. Default 0. Enable SPEECH output from Vcore if the monitor value exceeds the limit value. Write 1, enable SPEECH output. Default 0.
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7.21 Speech Control Register 2 Index 1Eh (Bank 0)
Power on default: 00h
BIT NAME ATTRIBUTE DESCRIPTION
7 6
Reserved EN_VR1_SPK
Reserved R/W
5
EN_VR0_SPK
R/W
4 3
EN_CASO_SPK EN_FAN3_SPK
R/W R/W
2
EN_NV5_SPK
R/W
1
EN_NV12_SPK
R/W
0
EN_V12_SPK
R/W
Reserved Enable SPEECH output from VINR1 if the monitor value exceeds the limit value. Write 1, enable SPEECH output. Default 0. Enable SPEECH output from VINR0 if the monitor value exceeds the limit value. Write 1, enable SPEECH output. Default 0. Enable SPEECH output from case open if the signal has gone high. Write 1, enable SPEECH output. Default 0. Enable SPEECH output from FAN 3 if the monitor value exceeds the limit value. Write 1, enable SPEECH output. Default 0. Enable SPEECH output from -5V if the monitor value exceeds the limit value. Write 1, enable SPEECH output. Default 0. Enable SPEECH output from -12V if the monitor value exceeds the limit value. Write 1, enable SPEECH output. Default 0. Enable SPEECH output from +12V if the monitor value exceeds the limit value. Write 1, enable SPEECH output. Default 0.
7.22 Speech Control Register 3 Index 1Fh (Bank 0)
Power on default: 00h
BIT NAME
Dis_SLOC_SPK
ATTRIBUTE
DESCRIPTION
7 6 5 4 3 2 1
R/W R/W R/W R/W R/W R/W R/W
Dis_ET5_SPK Dis_ET4_SPK Dis_ET3_SPK Dis_ET2_SPK Dis_ET1_SPK EN_VSB_SPK
0
EN_VBAT _SPK
R/W
Disable SPEECH output from SLOTOCC# if the CPU is absent. Write 1, disable SPEECH output. Default 0. Disable SPEECH output from EVNTRP5 if a transition occurs at pin. Write 1, disable SPEECH output. Default 0. Disable SPEECH output from EVNTRP4 if a transition occurs at pin. Write 1, disable SPEECH output. Default 0. Disable SPEECH output from EVNTRP3 if a transition occurs at pin. Write 1, disable SPEECH output. Default 0. Disable SPEECH output from EVNTRP2 if a transition occurs at pin. Write 1, disable SPEECH output. Default 0. Disable SPEECH output from EVNTRP1if a transition occurs at pin. Write 1, disable SPEECH output. Default 0. Enable SPEECH output from VSB if the monitor value exceeds the limit value. Write 1, enable SPEECH output. Default 0. Enable SPEECH output from VBAT if the monitor value exceeds the limit value. Write 1, enable SPEECH output. Default 0. Publication Release Date: April 14, 2006 Revision 1.1
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W83791D/G
7.23 Value RAM Index 20h- 3Fh (Bank 0)
ADDRESS A6-A0 DESCRIPTION
20h 21h 22h 23h 24h 25h 26h 27h 28h
VCOREA reading VINR0 reading +3.3VIN reading VDD 5V reading +12VIN reading -12VIN reading -5VIN reading Temperature reading FAN1 reading Note: This location stores the number of counts of the internal clock per revolution. FAN2 reading Note: This location stores the number of counts of the internal clock per revolution. FAN3 reading Note: This location stores the number of counts of the internal clock per revolution. VCOREA High Limit, default value is defined by Vcore Voltage +0.2v. VCOREA Low Limit, default value is defined by Vcore Voltage -0.2v. VINR0 High Limit. VINR0 Low Limit. +3.3VIN High Limit +3.3VIN Low Limit VDD 5V High Limit VDD 5V Low Limit +12VIN High Limit +12VIN Low Limit -12VIN High Limit -12VIN Low Limit -5VIN High Limit -5VIN Low Limit Temperature sensor 1 (VTIN1) High Limit Temperature sensor 1 (VTIN1) Hysteresis Limit
29h
2Ah
2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah
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Value RAM Index 20h- 3Fh (Bank 0), continued.
ADDRESS A6-A0
DESCRIPTION
3Bh
FAN1 Fan Count Limit Note: It is the number of counts of the internal clock for the Low Limit of the fan speed. FAN2 Fan Count Limit Note: It is the number of counts of the internal clock for the Low Limit of the fan speed. FAN3 Fan Count Limit Note: It is the number of counts of the internal clock for the Low Limit of the fan speed. Reserved
3Ch
3Dh
3E- 3Fh
Setting all ones to the high limits for voltages and fans (0111 1111 binary for temperature) means interrupts will never be generated except the case when voltages go below the low limits.
7.24 Configuration Register Index 40h (Bank 0)
Power on default <7:0> = 01h
BIT NAME ATTRIBUTE DESCRIPTION
7
Initialization
R/W
6 5 4 3
IRQ output
R/W R/W
IRQ Polarity Reserved INT_Clear
Set one restores power on default value to all registers except the Serial Bus Address register. This bit clears itself since the power on default is zero. Set 0, IRQ output level signal. Set 1, output pulse signal. Default is 0, but when set the IRQ as pulse output, it become to low pulse. When set to 0, IRQ active high. Set to 1, IRQ active low. Default is 0. Reserved A one disables the SMI# and IRQ# outputs without affecting the contents of Interrupt Status Registers. The device will stop monitoring. It will resume upon clearing of this bit. Note: The outputs of Interrupt pins will not be cleared if the user writes a zero to this location after an interrupt has occurred unlike "INT_Clear'' bit. A one enables the IRQ Interrupt output. A one enables the SMI# Interrupt output. A one enables startup of monitoring operations; a zero puts the part in standby mode. Note: The outputs of Interrupt pins will not be cleared if the user writes a zero to this location after an interrupt has occurred unlike "INT_Clear'' bit.
R/W
2 1 0
EN_IRQ EN_SMI# START
R/W R/W R/W
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7.25 Interrupt Status Register 1 Index 41h (Bank 0)
Power on default: 00h
BIT NAME ATTRIBUTE DESCRIPTION
7 6 5 4 3 2 1 0
FAN2 FAN1 TEMP2 TEMP1 5VDD +3.3VIN VINR0 Vcore
Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only
A one indicates the fan count limit of FAN2 has been exceeded. A one indicates the fan count limit of FAN1 has been exceeded. A one indicates a high limit of VTIN2 has been exceeded from temperature sensor 2. A one indicates a high limit of VTIN1 has been exceeded from temperature sensor 1. A one indicates a high or low limit of power 5VDD has been exceeded. A one indicates a high or low limit of +3.3VIN has been exceeded. A one indicates a high or low limit of VINR0 has been exceeded. A one indicates a high or low limit of Vcore has been exceeded.
7.26 Interrupt Status Register 2 Index 42h (Bank 0)
Power on default: 00h
BIT NAME ATTRIBUTE DESCRIPTION
7 6 5 4 3 2 1 0
Reserved VINR1 TEMP3 Chassis Intrusion FAN3 -5VIN -12VIN +12VIN Read Only Read Only Read Only Read Only Read Only Read Only Read Only
Reserved A one indicates a high or low limit of VINR1 (pin33) has been exceeded. A one indicates a high or low limit of VTIN3 has been exceeded from temperature sensor 3. A one indicates Chassis Intrusion has gone high. A one indicates the fan count limit of FAN3 has been exceeded. A one indicates a high or low limit of -5VIN has been exceeded. A one indicates a high or low limit of -12VIN has been exceeded. A one indicates a high or low limit of +12VIN has been exceeded.
Note: Interrupt status register III is defined at index 9Bh
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7.27 SMI# Mask Register 1 Index 43h (Bank 0)
Power on default: 00h
BIT NAME ATTRIBUTE DESCRIPTION
7 6 5 4 3 2 1 0
FAN2 FAN1 TEMP2 TEMP1 5VDD +3.3VIN VINR0 Vcore
R/W R/W R/W R/W R/W R/W R/W R/W
A one disables the corresponding interrupt status bit for SMI# interrupt A one disables the corresponding interrupt status bit for SMI# interrupt. A one disables the corresponding interrupt status bit for SMI# interrupt. A one disables the corresponding interrupt status bit for SMI# interrupt. A one disables the corresponding interrupt status bit for SMI# interrupt. A one disables the corresponding interrupt status bit for SMI# interrupt. A one disables the corresponding interrupt status bit for SMI# interrupt. A one disables the corresponding interrupt status bit for SMI# interrupt.
7.28 SMI# Mask Register 2 Index 44h (Bank 0)
Power on default: 00h
BIT NAME ATTRIBUTE DESCRIPTION
7 6 5 4 3 2 1 0
Reserved VINR1 TEMP3 Chassis Intrusion FAN3 -5VIN -12VIN +12VIN R/W R/W R/W R/W R/W R/W R/W
Reserved A one disables the corresponding interrupt status bit for SMI# interrupt. A one disables the corresponding interrupt status bit for SMI# interrupt. A one disables the corresponding interrupt status bit for SMI# interrupt. A one disables the corresponding interrupt status bit for SMI# interrupt. A one disables the corresponding interrupt status bit for SMI# interrupt. A one disables the corresponding interrupt status bit for SMI# interrupt. A one disables the corresponding interrupt status bit for SMI# interrupt.
Note: SMI# Mask register III is defined at index 9Ch
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W83791D/G
7.29 IRQ Mask Register 1 Index 45h (Bank 0)
Power on default: 00h
BIT NAME ATTRIBUTE DESCRIPTION
7 6 5 4 3 2 1 0
FAN2 FAN1 TEMP2 TEMP1 5VDD +3.3VIN VINR0 Vcore
R/W R/W R/W R/W R/W R/W R/W R/W
A one disables interrupt. A one disables interrupt. A one disables interrupt. A one disables interrupt. A one disables interrupt. A one disables interrupt. A one disables interrupt. A one disables interrupt.
the corresponding interrupt status bit for IRQ the corresponding interrupt status bit for IRQ the corresponding interrupt status bit for IRQ the corresponding interrupt status bit for IRQ the corresponding interrupt status bit for IRQ the corresponding interrupt status bit for IRQ the corresponding interrupt status bit for IRQ the corresponding interrupt status bit for IRQ
7.30 IRQ Mask Register 2 Index 46h (Bank 0)
Power on default: 00h
BIT NAME ATTRIBUTE DESCRIPTION
7
Chassis clear VINR1 TEMP3 Chassis Intrusion FAN3 -5VIN -12VIN +12VIN
R/W
A one outputs a minimum 20 ms active low pulse on the Case Open pin. The register bit self clears after the pulse has been output. A one disables the corresponding interrupt status bit for IRQ interrupt. A one disables the corresponding interrupt status bit for IRQ interrupt. A one disables the corresponding interrupt status bit for IRQ interrupt. A one disables the corresponding interrupt status bit for IRQ interrupt. A one disables the corresponding interrupt status bit for IRQ interrupt. A one disables the corresponding interrupt status bit for IRQ interrupt. A one disables the corresponding interrupt status bit for IRQ interrupt.
6 5 4 3 2 1 0
R/W R/W R/W R/W R/W R/W R/W
Note: IRQ mask register III is defined at index 9Dh
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7.31 VID/Fan Divisor Register Index 47h (Bank 0)
Power on default: 0101_xxxx
BIT NAME ATTRIBUTE DESCRIPTION
7-6
FAN2_DIV
R/W
FAN2 Speed Divisor. The third bit of FAN 2 divisor is defined in Index 5Dh. <7:6> = 00 - divide by 1; <7:6> = 01 - divide by 2 (Default); <7:6> = 10 - divide by 4; <7:6> = 11 - divide by 8. FAN1 Speed Control. The third bit of FAN 1 divisor is defined in Index 5Dh. <5:4> = 00 - divide by 1; <5:4> = 01 - divide by 2 (Default); <5:4> = 10 - divide by 4; <5:4> = 11 - divide by 8. The VID <3:0> inputs, which is latched when VDD 5V power good.
5-4
FAN1_DIV
R/W
3-0
VID <3:0>
Read only
Note: Please refer to Bank0 Index 5Dh, Fan divisor table.
7.32 Serial Bus Address Register Index 48h (Bank 0)
Power on default: 0010_11xx.
BIT NAME ATTRIBUTE DESCRIPTION
7 6-0
Reserved SMBADDR1 R/W
Reserved. Serial Bus Address <7:1> for general index registers. The address bit 0 and bit 1 are trapped by the pin 10 and pin 11, respectively.
7.33 Voltage ID (VID4) & Device ID Index 49h (Bank 0)
Power on default: 0001_000x
BIT NAME ATTRIBUTE DESCRIPTION
7-1
DID<6:0>
Read only
Device ID<6:0>, W83791D/G version ID that differentiates chip serial product number. This default value is 0010000b, that means is 1.0. The VID4 input, which is latched when VDD 5V power good.
0
VID4
Read only
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7.34 Temperature 2 and Temperature 3 Serial Bus Address Register Index4Ah (Bank 0)
Power on default: 01h; Reset by MR
BIT NAME ATTRIBUTE DESCRIPTION
7 6-4
DIS_T3 I2CADDR3
R/W R/W
Set to 1, disable temperature 3 sensor and can not access any data from Temperature Sensor 3. Temperature 3 Serial Bus Address. The serial bus address is 1001xxx. Where xxx are defined in these bits. Set to 1, disable temperature Sensor and cannot access any data from Temperature Sensor 2. Temperature 2 Serial Bus Address. The serial bus address is 1001xxx. Where xxx are defined in these bits.
3 2-0
DIS_T2 I2CADDR2
R/W R/W
7.35 Pin Control Register Index4Bh (Bank 0)
Power on default: 44h, Reset by MR.
BIT NAME ATTRIBUTE DESCRIPTION
7-6
FAN3_DIV
R/W
FAN3 Speed Divisor. The third bit of FAN 3 speed divisor is defined in Index 5Dh. <7:6> = 00 - divide by 1; <7:6> = 01 - divide by 2; <7:6> = 10 - divide by 4; <7:6> = 11 - divide by 8; Select A/D Converter Clock Input. <5:4> = 00 - default. ADC clock select 22.5 Khz. <5:4> = 01- ADC clock select 5.6 Khz. (22.5K/4) <5:4> = 10 - ADC clock select 1.4Khz. (22.5K/16) <5:4> = 11 - ADC clock select 0.35 Khz. (22.5K/64) Reserved
5-4
ADCOVSEL
R/W
3-0
Reserved
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7.36 SMI#/OVT# Property Select Index 4Ch (Bank 0)
Power on default: 01h
BIT NAME ATTRIBUTE DESCRIPTION
7-6
TEMP_SMI_MD [1:0]
R/W
5-4
OVT_MD[1:0]
R/W
3
EN_OVT3
R/W
Temperature SMI# Mode Select. <00> - Comparator Interrupt Mode: Temperature 1/2/3 exceeds TO (Over-temperature) limit causes and interrupt and this interrupt will be reset by reading all the Interrupt Staus. <01> - Two Time Interrupt Mode:(Default) This bit use in temperature sensor 1/2/3 interrupt mode with hysteresis type. Temperature exceeding TO, causes an interrupt and then temperature going below THYST will also cause an interrupt if the previous interrupt has been reset by reading all the interrupt Status Register. Once an interrupt event has occurred by exceeding TO, then reset, if the temperature remains above the THYST. <10> - One Time Interrupt Mode: This bit use in temperature sensor 1/2/3 interrupt mode with hysteresis type. Temperature exceeding TO (Overtemperature, defined in Bank 1/2) causes an interrupt and then temperature going below THYST (Hysteresis temperature, defined in Bank 1/2) will not cause an interrupt. Once an interrupt event has occurred by exceeding TO, then going below THYST, and interrupt will not occur again until the temperature exceeding TO. OVT# Mode Select. There are three OVT# signal output type. <00> - Comparator Mode: (Default) Temperature exceeding TO causes the OVT# output activated until the temperature is less than THYST. <01> - Interrupt Mode: Setting temperature exceeding TO causes the OVT# output activated indefinitely until reset reading temperature sensor 1/2/3 registers. Temperature exceeding TO, then OVT# reset, and then temperature going below THYST will also cause the OVT# activated indefinitely until reset by reading temperature sensor 1/2/3. Once the OVT# will not be activated by exceeding TO, then reset, if the temperature remains above THYST, the OVT# will not be activated again. <10> - ACPI Mode: If set to 1 then enable ACPI OVT# output. Which always send an OVT# signal when the temperature over the ACPI temperature increment value defined at Index 5Eh. Enable temperature sensor 3 over-temperature (OVT) output if set to 1. Default is 0, disable OVT2 output through pin OVT#. The pin OVT# is wire OR with OVT1 and OVT2.
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SMI#/OVT# Property Select Index 4Ch (Bank 0), continued.
BIT
NAME
ATTRIBUTE
DESCRIPTION
2
EN_OVT2
R/W
1
EN_OVT1
R/W
0
OVTPOL
R/W
Enable temperature sensor 2 over-temperature (OVT) output if set to 1. Default is 0, disable OVT2 output through pin OVT#. The pin OVT# is wire OR with OVT1 and OVT3. Enable temperature sensor 1 over-temperature (OVT) output .if set to 1. Default is 0, disable OVT1 output through pin OVT#. The pin OVT# is wire OR with OVT2 and OVT3. Over-Temperature Polarity. Write 0, OVT# active high. Write 1, OVT# active low. Default is 1.
7.37 FAN 1- 3 IN/OUT and BEEP Control Register Index 4Dh (Bank 0)
Power on default [7:0]: 0001_0101; Reset by MR.
BIT NAME ATTRIBUTE DESCRIPTION
7
DIS_ABN
R/W
6 5 4
Reserved FANOPV3 FANINC3
R/W R/W
3 2
FANOPV2 FANINC2
R/W R/W
1 0
FANOPV1 FANINC1
R/W R/W
Disable power-on abnormal the monitor voltage including Vcore, and +3.3V. If these voltages exceed the limit value, the pin of BEEP (Open Drain) will drives 300Hz and 600Hz frequency signal. Write 1, the frequency will be disable. Default 0. After power on, the system should set 1 to this bit to 1 in order to disable BEEP. Reserved. FAN 3 output value if FANINC3 sets to 0. Write 1, then pin 18 always generates logic high signal. Write 0, pin18 always generates logic low signal. This bit is 0. FAN3 Input Control. Set to 1, pin 18 acts as FAN clock input, which is default value. Set to 0, this pin 18 acts as FAN control signal and the output value of FAN control is set by this register bit 5. This output pin can connect to power PMOS gate to control FAN ON/OFF. FAN 2 output value if FANINC2 sets to 0. Write 1, then pin 19 always generates logic high signal. Write 0, pin 19 always generates logic low signal. This bit is 0. FAN2 Input Control. Set to 1, pin 19 acts as FAN clock input, which is default value. Set to 0, this pin 19 acts as FAN control signal and the output value of FAN control is set by this register bit 3. This output pin can connect to power NMOS gate to control FAN ON/OFF. FAN 1 output value if FANINC1 sets to 0. Write 1, then pin 20 always generates logic high signal. Write 0, pin20 always generates logic low signal. This bit is 0. FAN1 Input Control. Set to 1, pin 20 acts as FAN clock input, which is default value. Set to 0, this pin 20 acts as FAN control signal and the output value of FAN control is set by this register bit 1. This output pin can connect to power PMOS gate to control FAN ON/OFF.
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7.38 Bank Select Index 4Eh (Bank 0)
Power on default [7:0] 1000_0000b; Reset by MR.
BIT NAME ATTRIBUTE DESCRIPTION
7
HBACS
R/W
High byte access. Set to 1, access Register 4Fh high byte register. Set to 0, access Register 4Fh low byte register. Default 1. Reserved Set the three bit to <001> means select to Bank1.
6:3 2:0
Reserved BANKSEL R/W
7.39 Winbond Vendor ID Index 4Fh (Bank 0)
Power on default: A3h
BIT NAME ATTRIBUTE DESCRIPTION
7:0
Vendor ID
Read Only
Vendor ID low byte if CR4E.bit7=0. Default A3h. Vendor ID high byte if CR4E.bit7=1. Default 5Ch.
7.40 Winbond Test Register Index 50h - 55h (Bank 0)
These Registers is reserved for Winbond test only. Users do not use these registers.
7.41 BEEP Control Register 1 Index 56h (Bank 0)
Power on default: 00h
BIT NAME
EN_FAN2_BP EN_FAN1_BP
ATTRIBUTE
DESCRIPTION
7 6 5
R/W R/W R/W
Enable BEEP output from FAN 2 if the monitor value exceeds the limit value. Write 1, enable BEEP output. Default 0. Enable BEEP output from FAN 1 if the monitor value exceeds the limit value. Write 1, enable BEEP output. Default 0. Enable BEEP output from Temperature Sensor 2 if the monitor value exceeds the limit value. Write 1, enable BEEP output. Default 0. Enable BEEP output from Temperature Sensor 1 if the monitor value exceeds the limit value. Write 1, enable BEEP output. Default 0. Enable BEEP output from VDD (5V) if the monitor value exceeds the limit value. Write 1, enable BEEP output. Default 0. Enable BEEP output from 3.3V if the monitor value exceeds the limit value. Write 1, enable BEEP output. Default 0. Enable BEEP output from Temperature Sensor 3 if the monitor value exceeds the limit value. Write 1, enable BEEP output. Default 0. Enable BEEP output from Vcore if the monitor value exceeds the limit value. Write 1, enable BEEP output. Default 0. Publication Release Date: April 14, 2006 Revision 1.1
EN_T2_BP
4
EN_T1_BP
R/W
3
EN_V5_BP
R/W
2 1
EN_V33_BP EN_T3_BP
R/W R/W
0
EN_V25A_BP
R/W
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W83791D/G
7.42 BEEP Control Register 2 Index 57h (Bank 0)
Power on default: 80h
BIT NAME ATTRIBUTE DESCRIPTION
7 6
EN_GBP EN_VR1_BP
R/W R/W
Enable Global BEEP. Write 1, enable global BEEP output. Default 1. Write 0, disable all BEEP output. Enable BEEP output from VINR1 if the monitor value exceeds the limit value. Write 1, enable BEEP output. Default 0. Enable BEEP output from VINR0 if the monitor value exceeds the limit value. Write 1, enable BEEP output. Default 0. Enable BEEP output from case open if the signal has gone high. Write 1, enable BEEP output. Default 0. Enable BEEP output from FAN 3 if the monitor value exceeds the limit value. Write 1, enable BEEP output. Default 0. Enable BEEP output from -5V if the monitor value exceeds the limit value. Write 1, enable BEEP output. Default 0. Enable BEEP output from -12V if the monitor value exceeds the limit value. Write 1, enable BEEP output. Default 0. Enable BEEP output from +12V if the monitor value exceeds the limit value. Write 1, enable BEEP output. Default 0.
5
EN_VR0_BP
R/W
4 3
EN_CASO_BP EN_FAN3_BP
R/W R/W
2 1
EN_NV5_BP EN_NV12_BP
R/W R/W
0
EN_V12_BP
R/W
7.43 Chip ID Index 58h (Bank 0)
Power on default: 71h
BIT NAME ATTRIBUTE DESCRIPTION
7-0
CHIPID
Read Only
Winbond Chip ID. Read this register will return 71h.
7.44 Diode Selection Register Index 59h (Bank 0)
Power on default: 70h
BIT NAME ATTRIBUTE DESCRIPTION
7 6
Reserved SELPIIV3 R/W
Reserved. Temperature sensor diode 3. When set to 1, select Pentium II compatible Diode. Set to 0 to select 2N3904 Bipolar mode Temperature sensor diode 2. When set to 1, select Pentium II compatible Diode. Set to 0 to select 2N3904 Bipolar mode
5
SELPIIV2
R/W
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Diode Selection Register Index 59h (Bank 0) , continued.
BIT
NAME
ATTRIBUTE
DESCRIPTION
4
SELPIIV1
R/W
Temperature sensor diode 1. When set to 1, select Pentium II compatible Diode. Set to 0 to select 2N3904 Bipolar mode Reserved
3-0
Reserved
7.45 Reserved Index 5Ah - (Bank 0) 7.46 FANIN 4/5 Control Index 5Bh (Bank 0)
Power on default: 00h; Reset by MR.
BIT NAME ATTRIBUTE DESCRIPTION
7
FANINC5
R/W
FAN5 Input Control. Set to 1, pin 47 acts as FAN clock input. Set to 0, this pin 47 acts as FAN control signal, which is default value. This output pin can connect to power PMOS gate to control FAN ON/OFF. FAN4 Input Control. Set to 1, pin 46 acts as FAN clock input. Set to 0, this pin 46 acts as FAN control signal, which is default value. This output pin can connect to power PMOS gate to control FAN ON/OFF. Reserved
6
FANINC4
R/W
5:0
Reserved
7.47 FAN 4/5 Divisor Control Index 5Ch (Bank 0)
Power on default: 00h
BIT NAME ATTRIBUTE DESCRIPTION
7 6:4
FAN5_OB FAN_DIV5
R/W R/W
Enable Fan 5 as Output Buffer. Set to 1, FANPWM5 can drive logical high or logical low. FAN5 Speed Divisor. <6:4> = 000 - divide by 1(Default); <6:4> = 001 - divide by 2; <6:4> = 010 - divide by 4; <6:4> = 011 - divide by 8. <6:4> = 100 - divide by 16. <6:4> = 101 - divide by 32. <6:4> = 110 - divide by 64 <6:4> = 111 - divide by 128. Enable Fan 4 as Output Buffer. Set to 1, FANPWM4 can drive logical high or logical low.
3
FAN4_OB
R/W
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FAN 4/5 Divisor Control Index 5Ch (Bank 0) , continued
BIT
NAME
ATTRIBUTE
DESCRIPTION
2:0
FAN_DIV4
R/W
FAN4 Speed Divisor. <2:0> = 000 - divide by 1(Default); <2:0> = 001 - divide by 2; <2:0> = 010 - divide by 4; <2:0> = 011 - divide by 8. <2:0> = 100 - divide by 16. <2:0> = 101 - divide by 32. <2:0> = 110 - divide by 64 <2:0> = 111 - divide by 128.
7.48 VBAT Monitor Control Register Index 5Dh (Bank 0)
Power on default: 00h; Reset by MR.
BIT NAME ATTRIBUTE DESCRIPTION
7 6 5 4 3 2 1 0
FAN DIV3_B2 FANDIV2_B2 FANDIV1_B2 EN_ALARM_R SP BJTS3 BJTS2 BJTS1
EN_VBAT_MNT
R/W R/W R/W R/W R/W R/W R/W R/W
FAN 3 divisor Bit 2. The bit 1-0 is defined in the Index 4Bh. FAN 2 divisor Bit 2. The bit 1-0 is defined in the Index 47h. FAN 1 divisor Bit 2. The bit 1-0 is defined in the Index 47h. Enable Alarm Response if set to 1. Temperature Sensor 3 type selection. Set to 1, select bipolar sensor. Set to 0, select thermistor sensor. Temperature Sensor 2 type selection.Set to 1, select bipolar sensor. Set to 0, select thermistor sensor. Temperature sensor 1 type selection. Set to 1, select bipolar sensor. Set to 0, select thermistor sensor. Write 1, enable battery voltage monitor. Write 0, disable battery voltage monitor. If enable this bit, the monitor value is value after one monitor cycle. Note that the monitor cycle time is at least 300 ms for W83791D/G.
7.49 ACPI Temperature Increment Register Index 5Eh
Power on default: 05h; Reset by MR.
BIT NAME ATTRIBUTE DESCRIPTION
7 6-0
Reserved DIFFREG[6:0]
R/W
Reserved. ACPI Temperature Increment Register. If set to this register to non-zero value, the OVT# signal will be activated at pointer of the temperature of times of DIFFREG (i.e. DIFFREG*n, where n is non-zero integer). The default value is 5 degree C.
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7.50 Reserved Index 5Fh (Bank 0) 7.51 FAN 1 Pre-Scale Register Index 80h (Bank 0)
Power on default: 01h
BIT NAME ATTRIBUTE DESCRIPTION
7
PWM_CLK_SEL1
R/W
PWM 1 Input Clock Select. This bit select Fan 1 input clock to pre-scale divider. 0: 3MHz 1: 125 KHz Fan 1 Input Clock Pre-Scale. The divider of input clock is the number defined by pre-scale. Thus, writing 0 transfers the input clock directly to counter. The maximum divider is 128 (7Fh). 00h : divider is 1 01h : divider is 2 02h : divider is 3 : :
6-0
PRE_SCALE1[6:0]
R/W
PWM frequency = (Input clock / pre-scale) / 256
7.52 FAN 1 Duty Cycle Select Register 81h (Bank 0)
Power on default: FFh
BIT NAME ATTRIBUTE DESCRIPTION
7-0
F1_DC[7:0]
R/W
Fan 1 Duty Cycle. This 8-bit register determines the number of input clock cycles, out of 256-cycle period, during which the PWM output is high. During smart fan 1 control mode, read this register will return smart fan duty cycle. 00h: PWM output is always logical Low. FFh: PWM output is always logical High. XXh: PWM output logical High percentage is (XX/256*100%) during one cycle.
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7.53 FAN 2 Pre-Scale Register Index 82h (Bank 0)
Power on default: 01h
BIT NAME ATTRIBUTE DESCRIPTION
7
PWM_CLK_SEL2
R/W
PWM 2 Input Clock Select. This bit select Fan 2 input clock to pre-scale divider. 0: 3 MHz 1: 125 KHz Fan 2 Input Clock Pre-Scale. The divider of input clock is the number defined by pre-scale. Thus, writing 0 transfers the input clock directly to counter. The maximum divider is 128 (7Fh). 00h : divider is 1 01h : divider is 2 02h : divider is 3 : :
6-0
PRE_SCALE2[6:0]
R/W
PWM frequency = (Input clock / pre-scale) / 256
7.54 FAN2 Duty Cycle Select Register Index 83h (Bank 0)
Power on default: FFh
BIT NAME ATTRIBUTE DESCRIPTION
7-0
F2_DC[7:0]
R/W
Fan 2 Duty Cycle. This 8-bit register determines the number of input clock cycles, out of 256-cycle period, during which the PWM output is high. During smart fan 2 control mode, read this register will return smart fan duty cycle. 00h: PWM output is always logical Low. FFh: PWM output is always logical High. XXh: PWM output logical High percentage is XX/256*100% during one cycle.
7.55 FAN 1/2 Configuration Register Index 84h (Bank 0)
Power on default: 00h
BIT NAME ATTRIBUTE DESCRIPTION
7-6 5-4
Reserved FAN2_TYPE R/W
Reserved FAN 2 PWM Control Type. 00 - Manual PWM Control Mode. (Default) 01 - Thermal Cruise mode. 10 - Fan Speed Cruise Mode. 11 - Reserved.
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FAN 1/2 Configuration Register Index 84h (Bank 0), continued.
BIT
NAME
ATTRIBUTE
DESCRIPTION
3-2
FAN1_TYPE
R/W
FAN 1 PWM Control Type. 00 - Manual PWM Control, which is automatic PWM. (Default) 01 - Thermal Cruise mode. 10 - Fan Speed Cruise Mode. 11 - Reserved. Enable Fan 2 as Output Buffer. Set to 1, FANPWM2 can drive logical high or logical low. Default Pin 11 (PWMOUT2) is open-drain. Enable Fan 1 as Output Buffer. Set to 1, FANPWM1 can drive logical high or logical low. Default Pin 10 (PWMOUT1) is open-drain.
1
FAN2_OB
R/W
0
FAN1_OB
R/W
7.56 Fan 1 Target Temperature Register/Target Fan 1 Speed Control Register Index 85h (Bank 0)
Power on default: 00h VTIN1 target temperature register for Thermal Cruise mode.
BIT NAME ATTRIBUTE DESCRIPTION
7 6-0
Reserved FAN_TAR_T1[6:0] R/W
Reserved. Fan 1 Target Temperature. Only for Thermal Cruise mode. When the temperature 1 over the target temperature add tolerance temperature, the smart fan 1 duty cycle will up count until the duty cycle obtain to FFh.
Fan 1 target speed register for Fan Speed Cruise mode.
BIT NAME ATTRIBUTE DESCRIPTION
7-0
FAN_TAR_CNT1 [7:0]
R/W
Target Fan 1 Speed Control. Only for Fan Speed Cruise Mode. When the fan 1 monitored Fan 1 Count over the target Fan Count add tolerance, the fan duty cycle will up/down count until the duty cycle have been corresponding the monitored speed count.
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7.57 Fan 2 Target Temperature Register/Target Fan 2 Speed Control Register Index 86h (Bank 0)
Power on default: 00h VTIN2 target temperature register for Thermal Cruise mode.
BIT NAME ATTRIBUTE DESCRIPTION
7 6-0
Reserved FAN_TAR_T2 [6:0]
R/W R/W
Reserved. Fan 2 Target Temperature. Only for Thermal Cruise mode. When the temperature 2 over the target temperature add tolerance temperature, the smart fan 2 duty cycle will up count until the duty cycle obtain to FFh.
Fan 2 target speed register for Fan Speed Cruise mode.
BIT NAME ATTRIBUTE DESCRIPTION
7-0
FAN_TAR_CNT2 [7:0]
R/W
Target Fan 2 Speed Control. Only for Fan Speed Cruise Mode. When the fan 2 monitored Fan 2 Count over the target Fan Count add tolerance, the fan duty cycle will up/down count until the duty cycle have been corresponding the monitored speed count.
7.58 Tolerance of Fan1/2 Target Temperature or Speed Register Index 87h (Bank0)
Power on default: 00h Tolerance of VTIN1/2 target temperature register.
BIT NAME ATTRIBUTE DESCRIPTION
7-4 3-0
TOL_T2[3:0] TOL_T1[3:0]
R/W R/W
Tolerance of Fan 2 Target Temperature. Only for Thermal Cruise mode. Tolerance of Fan 1 Target Temperature. Only for Thermal Cruise mode.
Tolerance of Fan 1/2 target speed register.
BIT NAME ATTRIBUTE DESCRIPTION
7-4 3-0
TOL_FS2[3:0] TOL_FS1[3:0]
R/W R/W
Tolerance of Fan 2 Target Speed Count. Only for Fan Speed Cruise mode. Tolerance of Fan 1 Target Speed Count. Only for Fan Speed Cruise mode.
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7.59 Fan 1 PWM Stop Duty Cycle Register Index 88h (Bank 0)
Power on default: 01h
BIT NAME ATTRIBUTE DESCRIPTION
7-0
STOP_DC1[7:0]
R/W
In Thermal Cruise mode, PWM duty will be 0 if it decreases to under this value. This register should be written a non-zero minimum PWM stop duty cycle.
7.60 Fan 2 PWM Stop Duty Cycle Register 89h (Bank 0)
Power on default: 01h
BIT NAME ATTRIBUTE DESCRIPTION
7-0
STOP_DC2[7:0]
R/W
In Thermal Cruise mode, PWM duty will be 0 if it decreases to under this value. This register should be written a non-zero minimum PWM stop duty cycle.
7.61 Fan 1 Start-up Duty Cycle Register Index 8Ah (Bank 0)
Power on default: 01h
BIT NAME ATTRIBUTE DESCRIPTION
7-0
START_DC1[7:0]
R/W
In Thermal Cruise mode, PWM duty will increase from 0 to this register value to provide a minimum duty cycle to turn on the fan. This register should be written a fan start-up duty cycle.
7.62 Fan 2 Start-up Duty Cycle Register Index 8Bh (Bank 0)
Power on default: 01h
BIT NAME ATTRIBUTE DESCRIPTION
7-0
START_DC2[7:0]
R/W
In Thermal Cruise mode, PWM duty will increase from 0 to this register value to provide a minimum duty cycle to turn on the fan. This register should be written a fan start-up duty cycle.
7.63 Fan 1 Stop Time Register Index 8Ch (Bank 0)
Power on default: 3Ch
BIT NAME
STOP_TIME1[7:0]
ATTRIBUTE
DESCRIPTION
7-0
R/W
In Thermal Cruise mode, this register determines the time of which PWM duty is from stop duty cycle to 0 duty cycle. The unit of this register is 0.1 second. The default value is 6 seconds.
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7.64 Fan 2 Stop Time Register Index 8Dh (Bank 0)
Power on default: 3Ch
BIT NAME ATTRIBUTE DESCRIPTION
7-0
STOP_TIME2 [7:0]
R/W
In Thermal Cruise mode, this register determines the time of which PWM duty is from stop duty cycle to 0 duty cycle. The unit of this register is 0.1 second. The default value is 6 seconds.
7.65 Fan 1/2/3 Step Down Time Register Index 8Eh (Bank 0)
Power on default: 0Ah
BIT NAME ATTRIBUTE DESCRIPTION
7-0
STEP_DOWN_T[7:0]
R/W
The time interval, which is 0.1 second unit, to decrease PWM duty in Thermal Cruise mode.
7.66 Fan 1/2/3 Step Up Time Register Index 8Fh (Bank 0)
Power on default: 0Ah
BIT NAME ATTRIBUTE DESCRIPTION
7-0
STEP_UP_T[7:0]
R/W
The time interval, which is 0.1 second unit, to increase PWM duty in Thermal Cruise mode.
7.67 Temperature Sensor 1 (VTIN1) Offset Register Index 90h (Bank 0)
Power on default: 00h
BIT NAME ATTRIBUTE DESCRIPTION
7-6 5-0
Reserved OFFSET1[5:0] R/W
Reserved. Temperature 1 (VTIN1) base temperature. The temperature is added by both monitor value and offset value. 01,1111 => +31 degree C 01,1110 => +30 degree C : 00,0001 => +1 degree C 00,0000 => +0 degree C 11,1111 => -1 degree C 11,1110 => -2 degree C : 10,0000 => -32 degree
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7.68 Temperature Sensor 2 (VTIN2) Offset Register Index 91h (Bank 0)
Power on default: 00h
BIT NAME ATTRIBUTE DESCRIPTION
7-6 5-0
Reserved OFFSET2[5:0]
R/W R/W
Reserved. Temperature2 (VTIN2) base temperature. The temperature is added by both monitor value and offset value. 01,1111 => +31 degree C 01,1110 => +30 degree C : 00,0001 => +1 degree C 00,0000 => +0 degree C 11,1111 => -1 degree C 11,1110 => -2 degree C : 10,0000 => -32 degree
7.69 Temperature Sensor 3 (VTIN3) Offset Register Index 92h (Bank 0)
Power-on default: 00h
BIT NAME ATTRIBUTE DESCRIPTION
7-6 5-0
Reserved OFFSET3[5:0]
R/W R/W
Reserved. Temperature3 (VTIN3) base temperature. The temperature is added by both monitor value and offset value. 01,1111 => +31 degree C 01,1110 => +30 degree C : 00,0001 => +1 degree C 00,0000 => +0 degree C 11,1111 => -1 degree C 11,1110 => -2 degree C : 10,0000 => -32 degree
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7.70 FAN 3 Pre-Scale Register Index 93h (Bank 0)
Power on default: 01h
BIT NAME ATTRIBUTE DESCRIPTION
7
PWM_CLK_SEL3
R/W
PWM 3 Input Clock Select. This bit select Fan 3 input clock to pre-scale divider. 0: 3 MHz 1: 125 KHz Fan 3 Input Clock Pre-Scale. The divider of input clock is the number defined by pre-scale. Thus, writing 0 transfers the input clock directly to counter. The maximum divider is 128 (7Fh). 00h : divider is 1 01h : divider is 2 02h : divider is 3 : :
6-0
PRE_SCALE3[6:0]
R/W
PWM frequency = (Input clock / pre-scale) / 256
7.71 FAN 3 Duty Cycle Select Register Index 94h (Bank 0)
Power on default: FFh
BIT NAME ATTRIBUTE DESCRIPTION
7-0
F3_DC[7:0]
R/W
Fan 3 Duty Cycle. This 8-bit register determines the number of input clock cycles, out of 256-cycle period, during which the PWM output is high. During smart fan3 control mode, read this register would return smart fan duty cycle. 00h: PWM output is always logical Low. FFh: PWM output is always logical High. XXh: PWM output logical High percentage is (XX/256*100%) during one cycle.
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7.72 FAN 3 Configuration Register Index 95h (Bank 0)
Power on default: 00h
BIT NAME ATTRIBUTE DESCRIPTION
7
PWM3INV
RO
PWMOUT3 input value if PWMOUT3 as GPIn. Return `1', the pin 23 status is logic high signal. Read `0', pin23 is logic low signal. PWMOUT2 input value if PWMOUT2 as GPIn. Return `1', the pin 11 status is logic high signal. Read `0', pin11 is logic low signal. PWMOUT1 input value if PWMOUT1 as GPIn. Return `1', the pin 10 status is logic high signal. Read `0', pin10 is logic low signal. Reserved FAN 3 PWM Control Type. 00 - Manual PWM Control. (Default) 01 - Thermal Cruise mode. 10 - Fan Speed Cruise Mode. 11 - Reserved. Reserved Enable Fan 3 as Output Buffer. Set to 1, FANPWM3 can drive logical high or logical low. Default Pin 23 (PWMOUT3) is open-drain.
6
PWM2INV
RO
5
PWM1INV
RO
4 3-2
Reserved FAN3_TYPE
Reserved R/W
1 0
Reserve FAN3_OB
R/W R/W
7.73 Fan 3 Target Temperature Register/Target Fan 3 Speed Control Register Index 96h (Bank 0)
Power on default: 00h VTIN3 target temperature register for Thermal Cruise mode.
BIT NAME ATTRIBUTE DESCRIPTION
7 6-0
Reserved FAN_TAR_T3[6:0]
R/W R/W
Reserved. Fan 3 Target Temperature. Only for Thermal Cruise mode. When the temperature 3 over the target temperature add tolerance temperature, the smart fan 3 duty cycle will up count until the duty cycle obtain to FFh.
DESCRIPTION
Fan 3 target speed register for Fan Speed Cruise mode.
BIT NAME ATTRIBUTE
7-0
FAN_TAR_CNT3 [7:0]
R/W
Target Fan 3 Speed Control. Only for Fan Speed Cruise Mode. When the fan 3 monitored Fan 3 Count over the target Fan Count add tolerance, the fan duty cycle will up/down count until the duty cycle have been corresponding the monitored speed count. Publication Release Date: April 14, 2006 Revision 1.1
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7.74 Tolerance of Fan 3 Target Temperature or Speed Register Index 97h (Bank 0)
Power on default: 00h Tolerance of VTIN3 target temperature register
BIT NAME ATTRIBUTE DESCRIPTION
7
FAN3INV
RO
FAN 3 input value if FANINC3 sets to 1. Return `1', the pin 18 status is logic high signal. Read `0', pin18 is logic low signal. FAN 2 input value if FANINC2 sets to 1. Return `1', the pin 19 status is logic high signal. Read `0', pin19 is logic low signal. FAN 1 input value if FANINC1 sets to 1. Return `1', the pin 20 status is logic high signal. Read `0', pin20 is logic low signal. Reserved Tolerance of Fan 3 Target Temperature. Only for Thermal Cruise mode.
6
FAN2INV
RO
5
FAN1INV
RO
4 3-0
Reserved TOL_T3[3:0]
Reserved R/W
Tolerance of Fan 3 target speed register.
BIT NAME ATTRIBUTE DESCRIPTION
7
FAN3INV
RO
FAN 3 input value if FANINC3 sets to 1. Return `1', the pin 18 status is logic high signal. Read `0', pin18 is logic low signal. FAN 2 input value if FANINC2 sets to 1. Return `1', the pin 19 status is logic high signal. Read `0', pin19 is logic low signal. FAN 1 input value if FANINC1 sets to 1. Return `1', the pin 20 status is logic high signal. Read `0', pin20 is logic low signal. Reserved Tolerance of Fan 3 Target Speed Count. Only for Fan Speed Cruise mode.
6
FAN2INV
RO
5
FAN1INV
RO
4 3-0
Reserved TOL_FS3[3:0]
Reserved R/W
7.75 Fan 3 PWM Stop Duty Cycle Register Index 98h (Bank 0)
Power on default: 01h
BIT NAME
STOP_DC3[7:0]
ATTRIBUTE
DESCRIPTION
7-0
R/W
In Thermal Cruise mode, PWM duty will be 0 if it decreases to under this value. This register should be written a nonzero minimum PWM stop duty cycle.
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7.76 Fan 3 Start-up Duty Cycle Register Index 99h (Bank 0)
Power on default: 01h
BIT NAME ATTRIBUTE DESCRIPTION
7-0
START_DC3[7:0]
R/W
In Thermal Cruise mode, PWM duty will increase from 0 to this register value to provide a minimum duty cycle to turn on the fan. This register should be written a fan start-up duty cycle.
7.77 Fan 3 Stop Time Register Index 9Ah (Bank 0)
Power on default: 3Ch
BIT NAME
STOP_TIME3[7:0]
ATTRIBUTE
DESCRIPTION
7-0
R/W
In Thermal Cruise mode, this register determines the time of which PWM duty is from stop duty cycle to 0 duty cycle. The unit of this register is 0.1 second. The default value is 6 seconds.
7.78 Interrupt Status Register III Index 9Bh (Bank 0)
Power on default: 00h
BIT NAME ATTRIBUTE DESCRIPTION
7 6 5 4 3 2
Reserved FAN5 FAN4 VBAT VSB TART3 Read Only Read Only Read Only Read Only Read Only
Reserved. A one indicates the fan count limit of FAN5 has been exceeded. A one indicates the fan count limit of FAN4 has been exceeded. A one indicates a high or low limit of VBAT has been exceeded. A one indicates a high or low limit of VSB has been exceeded. Target Temperature 3 Status. A one indicates VTIN3 with Fan 3 full speed can not be in the specific range after 3 minutes. Target Temperature 2 Statue. A one indicates VTIN2 temperature with Fan 2 full speed can not be in the specific range after 3 minutes. Target Temperature 1 Statue. A one indicates VTIN1 temperature with Fan 1 full speed can not be in the specific range after 3 minutes.
1
TART2
Read Only
0
TART1
Read Only
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7.79 SMI# Mask Register III Index 9Ch (Bank 0)
Power on default: 00h
BIT NAME ATTRIBUTE DESCRIPTION
7 6 5 4 3 2 1 0
Reserved FAN5 FAN4 VBAT VSB TART3 TART2 TART1 R/W R/W R/W R/W R/W R/W R/W
Reserved. A one disables the corresponding interrupt status bit for SMI# interrupt. A one disables the corresponding interrupt status bit for SMI# interrupt. A one disables the corresponding interrupt status bit for SMI# interrupt. A one disables the corresponding interrupt status bit for SMI# interrupt. A one disables the corresponding interrupt status bit for SMI# interrupt. (Target temperature 3) A one disables the corresponding interrupt status bit for SMI# interrupt. (Target temperature 2) A one disables the corresponding interrupt status bit for SMI# interrupt. (Target temperature 1)
7.80 Interrupt Mask Register III Index 9Dh (Bank 0)
Power on default: 00h
BIT NAME ATTRIBUTE DESCRIPTION
7 6 5 4 3 2 1 0
Reserved FAN5 FAN4 VBAT VSB TART3 TART2 TART1 R/W R/W R/W R/W R/W R/W R/W
Reserved. A one disables the corresponding interrupt status bit for IRQ interrupt. A one disables the corresponding interrupt status bit for IRQ interrupt. A one disables the corresponding interrupt status bit for IRQ interrupt. A one disables the corresponding interrupt status bit for IRQ interrupt. A one disables the corresponding interrupt status bit for IRQ interrupt. (Target temperature 3) A one disables the corresponding interrupt status bit for IRQ interrupt. (Target temperature 2) A one disables the corresponding interrupt status bit for IRQ interrupt. (Target temperature 1)
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7.81 FAN4_PRE_SCALE register Index 9Eh (Bank 0)
Power on default: 01h
BIT NAME ATTRIBUTE DESCRIPTION
7
PWM_CLK_SEL4
R/W
PWM 4 Input Clock Select. This bit select Fan 4 input clock to pre-scale divider. 0: 3 MHz 1: 125 KHz Fan 4 Input Clock Pre-Scale. The divider of input clock is the number defined by pre-scale. Thus, writing 0 transfers the input clock directly to counter. The maximum divider is 128 (7Fh). 00h : divider is 1 01h : divider is 2 02h : divider is 3 : :
6:0
PRE_SCALE4 [6:0]
R/W
PWM frequency = (Input clock / pre-scale) / 256
7.82 FAN5_PRE_SCALE register Index 9Fh (Bank 0)
Power on default: 01h
BIT NAME ATTRIBUTE DESCRIPTION
7
PWM_CLK_SEL5
Read /Write
PWM 5 Input Clock Select. This bit select Fan 5 input clock to pre-scale divider. 0: 3 MHz 1: 125 KHz Fan 5 Input Clock Pre-Scale. The divider of input clock is the number defined by pre-scale. Thus, writing 0 transfers the input clock directly to counter. The maximum divider is 128 (7Fh). 00h : divider is 1 01h : divider is 2 02h : divider is 3 : :
6:0
PRE_SCALE5[6:0]
Read /Write
PWM frequency = (Input clock / pre-scale) / 256
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W83791D/G
7.83 FAN 4 Duty Cycle Select Register--A0h (Bank 0)
Power on default: FFh
BIT NAME ATTRIBUTE DESCRIPTION
7-0
F4_DC[7:0]
R/W
Fan 4 Duty Cycle. This 8-bit register determines the number of input clock cycles, out of 256-cycle period, during which the PWM output is high. During smart fan3 control mode, read this register would return smart fan duty cycle. 00h: PWM output is always logical Low. FFh: PWM output is always logical High. XXh: PWM output logical High percentage is (XX/256*100%) during one cycle.
7.84 FAN 5 Duty Cycle Select Register--A1h (Bank 0)
Power on default: FFh
BIT NAME ATTRIBUTE DESCRIPTION
7-0
F5_DC[7:0]
R/W
Fan 5 Duty Cycle. This 8-bit register determines the number of input clock cycles, out of 256-cycle period, during which the PWM output is high. During smart fan3 control mode, read this register would return smart fan duty cycle. 00h: PWM output is always logical Low. FFh: PWM output is always logical High. XXh: PWM output logical High percentage is (XX/256*100%) during one cycle.
7.85 BEEP Control Register 3 Index A3h (Bank 0)
Power on default: 00h ; Reset by MR.
BIT NAME ATTRIBUTE DESCRIPTION
7 6 5
EN_USER_ BP FAN5_BP FAN4_BP
R/W R/W R/W
User defines BEEP output function. Write 1, the BEEP is always active. Write 0, this function is inactive. (Default 0) Enable BEEP output from FAN5 Write 1; enable BEEP output. Set 0 (default value), it will be disable BEEP tone output. Enable BEEP output from FAN4. Write 1; enable BEEP output. Set 0 (default value), it will be disable BEEP tone output. Enable BEEP output from Target temperature 3. Write 1; enable BEEP output. Set 0 (default value), it will be disable BEEP tone output. Enable BEEP output from Target temperature 2. Write 1; enable BEEP output. Set 0 (default value), it will be disable BEEP tone output.
4
EN_TART3 _BP EN_TART2 _BP
R/W
3
R/W
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BEEP Control Register 3 Index A3h (Bank 0) , continued
BIT
NAME
ATTRIBUTE
DESCRIPTION
2
EN_TART1_BP R/W
Enable BEEP output from Target temperature 1. Write 1; enable BEEP output. Set 0 (default value), it will be disable BEEP tone output. Enable BEEP output from V-Core B. Write 1; enable BEEP output, which is default value. Enable BEEP Output from V-Core A if the monitor value exceeds the limits value. Write 1, enable BEEP output, which is default value.
1 0
EN_VBAT_BP EN_VSB_BP
R/W R/W
7.86 Speech Flash Memory Read Data Registers Index A4h-A5h (Bank 0)
Power on default: 00h
INDEX NAME ATTRIBUTE DESCRIPTION
A4h A5h
SPEECHRD2 SPEECHRD3
RO RO
Speech Flash Read Data 2. Speech flash reading data bits [23:16]. Speech Flash Read Data 3. Speech flash reading data bits [31:24].
7.87
BIT
EVNTRAP1- 5 and GPIO 5-9 Select Index A6h (Bank 0)
NAME ATTRIBUTE DESCRIPTION
Power on default: 00h 7 6 5 4 3 2 1 0 GPIO_SEL SMI_LEDOUT Reserved EVNT5_GPIO9 EVNT4_GPIO8 EVNT3_GPIO7 EVNT2_GPIO6 EVNT1_GPIO5 R/W R/W Reserved R/W R/W R/W R/W R/W Write `1' select to pin 1 as GPIO9 function when using speech. Default is `0'. Note: Index 15h bit6='0' if use GPIO function at this pin. Write `1' select to pin 48 as GPIO8 function when using speech. Default is `0'. Note: Index 15h bit6='0' if use GPIO function at this pin. Write `1' select to pin 47 as GPIO7 function when using speech. Default is `0'. Note: Index 15h bit6='0' if use GPIO function at this pin. Write `1' select to pin 46 as GPIO6 function when using speech. Default is `0'. Note: Index 15h bit6='0' if use GPIO function at this pin. Write `1' select to pin 45 as GPIO5 function when using speech. Default is `0'. Write `1' to this bit then read it, if return `0' means speech function else means GPIO function. Select SMI# or LEDOUT function at pin 44. Default is SMI# function.
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W83791D/G
7.88 Flash Page count Index A7h (Bank 0)
Power on default: 00h; Reset by MR.
BIT NAME ATTRIBUTE DESCRIPTION
7-5 4-0
Reserved Page count RO
Reserved Flash (W55FXX) size of each page is 512K, so read these bits may know the flash size when finish page coding program.
7.89 Real Time Hardware Status Register I Index A9h (Bank 0)
Power on default: 00h; Reset by MR.
BIT NAME ATTRIBUTE DESCRIPTION
7 6 5 4 3 2 1 0
FAN2 FAN1 TEMP2 TEMP1 5VDD +3.3VIN VINR0 Vcore
Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only
Set 1, the fan speed counter is over the limit value. Set 0, the fan speed counter is in the limit range. Set 1, the fan speed counter is over the limit value. Set 0, the fan speed counter is in the limit range. Set 1, the voltage of temperature sensor is over the limit value. Set 0, the voltage of temperature sensor is in the limit range. Set 1, the voltage of temperature sensor is over the limit value. Set 0, the voltage of temperature sensor is in the limit range. Set 1, the voltage of +5V is over the limit value. Set 0, the voltage of +5V is in the limit range. Set 1, the voltage of +3.3V is over the limit value. Set 0, the voltage of +3.3V is in the limit range. Set 1, the voltage of VINR0 is over the limit value. Set 0, the voltage of VINR0 is in the limit range. Set 1, the voltage of VCORE is over the limit value. Set 0, the voltage of VCORE is in the limit range.
7.90 Real Time Hardware Status Register II Index AAh (Bank 0)
Power on default: 00h; Reset by MR.
BIT NAME ATTRIBUTE DESCRIPTION
7 6 5 4
Revered VINR1 TEMP3 Chassis Intrusion
Read Only Read Only Read Only Read Only
Reserved. Set 1, the voltage of VINR1 is over the limit value. Set 0, the voltage of VINR1 is in the limit range. Set 1, the voltage of temperature sensor is over the limit value. Set 0, the voltage of temperature sensor is in the limit range. Set 1, the case open sensor is sensed the high value. Set 0, the case open signal is low.
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Real Time Hardware Status Register II Index AAh (Bank 0), continued.
BIT
NAME
ATTRIBUTE
DESCRIPTION
3 2 1 0
FAN3 -5VIN -12VIN +12VIN
Read Only Read Only Read Only Read Only
Set 1, the fan speed counter is over the limit value. Set 0, the fan speed counter is during the limit range. Set 1, the voltage of -5V is over the limit value. Set 0, the voltage of -5V is during the limit range. Set 1, the voltage of -12V is over the limit value. Set 0, the voltage of -12V is during the limit range. Set 1, the voltage of +12V is over the limit value. Set 0, the voltage of +12V is in the limit range.
7.91 Real Time Hardware Status Register III Index ABh (Bank 0)
Power on default: 00h; Reset by MR.
BIT NAME ATTRIBUTE DESCRIPTION
7 6 5 4 3 2
Reserved FAN5 FAN4 VBAT VSB TART3 Read Only Read Only Read Only Read Only Read Only
Reserved. Set 1, the fan speed counter is over the limit value. Set 0, the fan speed counter is during the limit range. Set 1, the fan speed counter is over the limit value. Set 0, the fan speed counter is during the limit range. Set 1, the voltage of VBAT is over the limit value. Set 0, the voltage of VBAT is during the limit range. Set 1, the voltage of VSB is over the limit value. Set 0, the voltage of VSB is in the limit range. Set 1, when target temperature 3 with Fan 3 full speed can not be in the range after 3 minutes. Set 0, the temperature or speed is in the specific range. Set 1, when target temperature 2 with Fan 2 full speed can not be in the range after 3 minutes. Set 0, the temperature or speed is in the specific range. Set 1, when target temperature 1 with Fan 3 full speed can not be in the range after 3 minutes. Set 0, the temperature or speed is in the specific range.
1
TART2
Read Only
0
TART1
Read Only
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W83791D/G
7.92 Revered Index AC - AFh (Bank 0) 7.93 Value RAM 2 Index B0h - B7h (BANK 0)
ADDRESS A6-A0 AUTO-INCREMENT DESCRIPTION
B0h B1h B2h B3h B4-B5h B6-7h B8-B9h BAh BBh BC BD BE-BFh
5VSB reading VBAT reading VINR1 reading Reserved 5VSB High/Low Limit VBAT High/ Low Limit VINR1 High/ Low Limit. FAN4 count reading FAN5 count reading FAN4 limit count FAN5 limit count Revered
7.94 Temperature Sensor 2 Temperature (High Byte) Register Index C0h (Bank 0)
BIT NAME ATTRIBUTE DESCRIPTION
7-0
TEMP2<8:1>
Read Only
Temperature <8:1> of VTIN 2, which is high byte.
7.95 Temperature Sensor 2 Temperature (Low Byte) Register Index C1h (Bank 0)
BIT NAME ATTRIBUTE DESCRIPTION
7 6-0
TEMP2<0> Reserved
Read Only Read Only
Temperature <0> of VTIN2, which is low byte. Read 0.
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7.96 Temperature Sensor 2 Configuration Register Index C2h (Bank 0)
Power on default: 00h; Reset by MR
BIT NAME ATTRIBUTE DESCRIPTION
7-5 4-3 2:1 0
Reserved FAULT Reserved STOP2 R/W R/W
Reserved Number of faults to detect before setting OVT# output to avoid false tripping due to noise. Reserved When set to 1 the sensor will stop monitor.
7.97 Temperature Sensor 2 Hysteresis (High Byte) Register Index C3h (Bank 0)
Power on default: 4Bh; Reset by MR
BIT NAME ATTRIBUTE DESCRIPTION
7-0
THYST2<8:1>
R/W
Temperature hysteresis bit 8-1, which is High Byte. The temperature default 75 degree C.
7.98 Temperature Sensor 2 Hysteresis (Low Byte) Register Index C4h (Bank 0)
Power on default: 00h; Reset by MR
BIT NAME ATTRIBUTE DESCRIPTION
7 6-0
THYST2<0> Reserved
R/W Read Only
Temperature hysteresis bit 0, which is low Byte. Read 0
7.99 Temperature Sensor 2 Over-temperature (High Byte) Register Index C5h (Bank 0)
Power on default: 50h; Reset by MR
BIT NAME ATTRIBUTE DESCRIPTION
7-0
TOVF2<8:1>
R/W
Over-temperature bit 8-1, which is High Byte. The temperature default 80 degree C.
7.100 Temperature Sensor 2 Over-temperature (Low Byte) Register Index C6h (Bank 0)
Power on default: 00h; Reset by MR.
BIT NAME ATTRIBUTE DESCRIPTION
7 6-0
TOVF2<0> Reserved
R/W Read Only
Over-temperature bit 0, which is low Byte. Read 0
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7.101 Temperature Sensor 3 Temperature (High Byte) Register Index C8h (Bank 0)
BIT NAME ATTRIBUTE DESCRIPTION
7-0
TEMP3<8:1>
Read Only
Temperature <8:1> of VTIN3, which is high byte.
7.102 Temperature Sensor 3 Temperature (Low Byte) Register Index C9h (Bank 0)
BIT NAME ATTRIBUTE DESCRIPTION
7 6-0
TEMP3<0> Reserved
Read Only Read Only
Temperature <0> of VTIN3, which is low byte. Read 0.
7.103
BIT
Temperature Sensor 3 Configuration Register Index CAh (Bank 0)
NAME ATTRIBUTE DESCRIPTION
Power on default: 00h; Reset by MR. 7-5 4-3 2:1 0 Reserved FAULT Reserved STOP3 R/W R/W R/W Reserved Number of faults to detect before setting OVT# output to avoid false tripping due to noise. Reserved When set to 1 the sensor will stop monitor.
7.104 Temperature Sensor 3 Hysteresis (High Byte) Register Index CBh (Bank 0)
Power on default: 4Bh; Reset by MR.
BIT NAME ATTRIBUTE DESCRIPTION
7-0
THYST3<8:1>
R/W
Temperature hysteresis bit 8-1, which is High Byte. The temperature default 75 degree C.
7.105 Temperature Sensor 3 Hysteresis (Low Byte) Register Index CCh (Bank 0)
Poweron default: 00h; Reset by MR.
BIT NAME ATTRIBUTE DESCRIPTION
6-0 7
Reserved THYST3<0>
Read Only R/W
Read 0 Temperature hysteresis bit 0, which is low Byte.
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7.106 Temperature Sensor 3 Over-temperature (High Byte) Register Index CDh (Bank 0)
Power on default: 50h; Reset by MR.
BIT NAME ATTRIBUTE DESCRIPTION
7-0
OVTF3<8:1>
R/W
Over-temperature bit 8-1, which is High Byte. The temperature default 80 degree C.
7.107 Temperature Sensor 3 Over-temperature (Low Byte) Register Index CEh (Bank 0)
Power on default: 00h; Reset by MR.
BIT NAME ATTRIBUTE DESCRIPTION
7 6-0
OVTF3<0> Reserved
R/W
Over-temperature bit 0, which is low Byte. Reserved
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8. ARP (ADDRESS RESOLUTION PROTOCOL) USE REGISTER DEFINED 8.1 Unique Device Identifier (UDID) -- 20h-2Fh (Bank 1)
In order to provide a mechanism to isolate each device for the purpose of address assignment each device must implement a unique device identifier (UDID). This 128-bit number is comprised of the following fields: 1 Byte Device Capabilities Bank 1 Index 20h 1 Byte Version/ Revision Bank 1 Index 21h 2 Byte 2 Byte 2 Byte Interface Bank 1 26h-27h 2 Byte Subsystem Vendor ID Bank 1 28h-29h 2 Byte Subsystem Device ID Bank 1 2Ah-2Bh 4 Byte Vendor Specific ID Bank 1 2Ch-2Fh
Vendor ID Device ID Bank 1 22h-23h Bank 1 24h-25h
INDEX
ATTRIBUTE
DESCRIPTIONS
20h 21h 22-23h 24-25h 26-27h
R/W R/W R/W R/W R/W
Device Capabilities (DEV_CAP capabilities. See detail SMBus 2.0.
[7:0]).
Describes
the
device's
Version/Revision (VERSION [7:0]). UDID version number and silicon revision identification. See detail SMBus2.0 Tues. Vendor ID (VENDOR_ID [15:0]). The device manufacturer's ID as assigned by the SBS Implementers' Forum or the PCI SIG. Device ID (DEV_ID [15:0]). The device ID as assigned by the device manufacturer (identified by the Vendor ID field). Interface (INTERFACE [15:0]). Identifies the protocol layer interfaces supported over the SMBus connection by the device. For example, ASF and IPMI. Subsystem Vendor ID (SVENDOR_ID [15:0]). This field may hold a value derived from any of several sources: 1. The device manufacturer's ID as assigned by the SBS Implementers' Forum or the PCI SIG. 2. The device OEM's ID as assigned by the SBS Implementers' Forum or the PCI SIG. 3. A value that, in combination with the Subsystem Device ID, can be used to identify an organization or industry group that has defined a particular common device interface specification. Subsystem Device ID (SDEV_ID [15:0]). The subsystem ID identifies a specific interface, implementation, or device. The Subsystem ID is defined by the party identified by the Subsystem Vendor ID field. Vendor Specific ID (SPEC_ID [31:0]). A unique number per device. See detail SMBus 2.0.
28-29h
R/W
2A-2Bh
R/W
2C-2Fh
R/W
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8.2 ASF Sensor Environmental Event
The document in ASF specification version 0.73 has indicated the listed table is presented as a guide only (Section 3.3.5.1 Page 8). It is not intended to represent a complete list of the possible environmental events from a system. The definition of the Event is shown as follow.
8.2.1 Temperature: Get Event Data message In the W83791D/G, it has three temperatures for monitoring System Board, CPU1, and CPU2. The listed table show that have the entity ID, entity instance, event source type, event type, event offset, and so on.
ASF PACKET DATA TEMPERATURE 1
Event sensor type Event type Event offset
0x01 (Temperature sensor) Threshold-based: 0x01h. The W83971D/G does not implement "generic severity".
Event Status: 011b (Asserted, Send) (iii) Upper Temp. 0x01:Threshold-based 0x09: Upper critical going high Event Status: 011b (Asserted, Send) (v) (iv)
0x01:Threshold-based 0x08: Upper Critical, going low (Reserved)
0x01:Threshold-based 0x02: Lower critical, going low
(ii)
0x01:Threshold-based 0x07: Upper non-critical going high Lower Temp
0x01:Threshold-based (i) 0x01:Threshold-based 0x01: Lower Non-critical Going high (Reserved) (vi) 0x00: Lower non-critical, going low
Event Status: 010b (Deasserted, Send)
Event sensor type: 0x01 (Temperature) Event Type: 0x01 (Threshold-based)
Event source type Sensor device
The W83791D/G is complying ASF 1.0 specification and the value is 0x68. The ASF specification indicates that the Sensor Device is the SMBus address of the sensor that caused the event for the PET Frame. Therefore, the Sensor Device of the W83791D/G is APR assigned address. Temperature 1: 0Eh (Don't use 00h and FFh. Therefore 01h Temperature 2: 0Fh Temperature 3: 10h VIN0).
Sensor number
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Temperature: Get Event Data message, continued.
ASF PACKET DATA
TEMPERATURE 1
Entity ID
Temperature 1: 07h (System board) Temperature 2/3: 03h (Processor) These are defined in Table 28-11 of IPMI v1.0 specification. This value is programmable because that may be used in add-in-card or connected to other device. Temperature 1: 01h (main system board). Temperature 2: 01h (Processor 1) Temperature 3: 02h (Processor 2) These are programmable. Temperature 1: 0Dh (zero-based) Temperature 2: 0Eh Temperature 3: 0Fh Status Value Status type Description Byte Count 0Bh
Entity instance
Event status index
Event status
0000_0010b Deasserted (send) Refer as above figure. 0000_0011b Asserted (send) 0000_0111b Event Status End
W83791D/G will respond 0Bh all relative information. When event status index 02h is more than 10h, the machine will be ended the transmission.
The reference table of ASF 0.64 is shown as following. Event Severity Monitor (0x01): That is represented the monitored temperature is under the lower temperature. Non Critical (0x08): that is represented the temperature is located between the lower and upper temperature. Critical Condition (0x10): that is represented the monitored temperature is over the upper temperature.
Critical Condition (0x10) Upper Temp. Non Critical (0x08) Lower Temp. Monitor (0x01)
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Entity ID and Instance (Default):
ENTITY ID ENTITY INSTANCE (PROGRAMMABLE) (PROGRAMMABLE) SENSOR IN W83791D/G EVENT EVENT STATUS NUMBER INDEX EVENT SENSOR TYPE
07h (System Board) 01h 01h 01h 01h 01h 01h 01h 01h 01h 01h 03h (Processor) 01h 01h 01h 02h 02h 02h 23h (System Chassis) 01h
+3.3VIN +5VIN +12VIN -12VIN -5VIN VSB VBAT VINR0 FAN1 Temperature1 VCORE FAN2 Temperature 2 VINR1 FAN3 Temperature 3 Case Intrusion
02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Dh 00h 0Bh 0Eh 01h 0Ch 0Fh 10h
03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Eh 01h 0Ch 0Fh 02h 0Dh 10h 11h
02h (Voltage) 02h 02h 02h 02h 02h 02h 02h 04h (Fan) 01h (Temperature) 02h 04h 01h 02h 04h 01h 05h (Chassis Intrusion)
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8.2.2 Voltage: Get Event Data message In the W83791D/G, it has three temperatures for monitoring System Board, CPU1, and CPU2. The listed table show that have the entity ID, entity instance, event source type, event type, event offset, and so on.
ASF PACKET DATA VOLTAGE INPUT
Event sensor type Event type Event offset
02h (Voltage sensor) Discrete (Generic Severity): 07h
(i) 07h: Discrete (Generic Severity) 02h: Transition to Critical from less severe Event Status: 011b (Asserted, send) High voltage 07h: Discrete (Generic Severity) 07h: Monitor Low voltage Event Status: 010b (Deasserted, send) 07h: Discrete (Generic Severity) (ii) 02h: Transition to Critical from less severe Event Status: 011b (Asserted, send)
Event sensor type: 02h (Voltage) Event Type: 07h (Discrete, Generic Severity)
Event source type Sensor device
The W83791D/G is complying ASF 1.0 specification and the value is 0 x 68. The ASF specification indicates that the Sensor Device is the SMBus address of the sensor that caused the event for the PET Frame. Therefore, the Sensor Device of the W83791D/G is APR assigned address. The number is shown as following: Voltage Sensor VCORE VINR0 +3.3VIN +5VIN +12VIN -12VIN -5VIN VSB VBAT VINR1 Sensor Number 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah
Sensor number
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Voltage: Get Event Data message, continued.
ASF PACKET DATA
VOLTAGE INPUT
Entity ID
The Entity ID is shown as following. Voltage Sensor Entity ID VCORE 03h (Processor) VINR0 07h (System board) +3.3VIN +5VIN +12VIN -12VIN -5VIN VSB VBAT VINR1 03h (Processor) These ID are defined in Table 28-11 of IPMI v1.0 specification. This value is programmable because that may be used in add-in-card or connected to other device. The Entity Instance is shown as following. Sensor Entity Instance VCORE 01h (Processor 1) VINR0 01h (Main system board) +3.3VIN +5VIN +12VIN -12VIN -5VIN VSB VBAT VINR1 02h (Processor 2) VCORE: 00h VINR0: 01h +3.3VIN: 02h +5VIN : 03h +12VIN: 04h -12VIN: 05h -5VIN: 06h VSB: 07h VBAT: 08h VINR1: 09h
Entity instance
Event status index
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Voltage: Get Event Data message, continued.
ASF PACKET DATA
VOLTAGE INPUT
Event status
Event Severity
0Bh W83791D/G will respond 0Bh all relative information. 0000_0111b Event Status End When event status index 02h is more than 0Fh, the machine will be ended the transmission. The reference table of ASF 0.64 is shown as following. Monitor (0x01): That is represented the monitored voltage is during the limit value. Critical Condition (0x10): that is represented the monitored voltage is over the limit value.
Critical Condition (0x10) Upper Volt. Monitor (0x01) Lower Volt. Critical Condition (0x10)
Status type Status Value 0000_0010b Desserted (send) 0000_0011b Asserted (send)
Description
Byte Count
8.2.3 Fan: Get Event Data message In the W83791D/G, it has three temperatures for monitoring System Board, CPU1, and CPU2. The listed table show that have the entity ID, entity instance, event source type, event type, event offset, and so on.
ASF PACKET DATA FAN CLOCK INPUT
Event sensor type Event type Event offset
04h (Fan speed sensor) Discrete (Generic Severity): 07h
(i) 05h: 'digital' Discrete (Generic Severity) 00h: Limit Not Exceeded Event Status: 010b (Deasserted, send) High Speed (Low Count) Fan Limit Lower Speed (High Count) Event Status: 011b (Asserted, send) 05h: 'digital' Discrete (Generic Severity) 01h: Limit Exceeded
Event sensor type: 04h (Fan) Event Type: 05h ('digital ' Discrete, Generic Severity)
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Fan: Get Event Data message, continued.
ASF PACKET DATA
FAN CLOCK INPUT
Event source type Sensor device
Sensor number
The W83791D/G is complying ASF 1.0 specification and the value is 0 x 68. The ASF specification indicates that the Sensor Device is the SMBus address of the sensor that caused the event for the PET Frame. Therefore, the Sensor Device of the W83791D/G is APR assigned address. The number is shown as following: Fan Sensor Sensor Number FAN 1 0Bh FAN 2 0Ch FAN 3 0Dh The Entity ID is shown as following. Voltage Sensor Entity ID (default) FAN 1 07h (System board) FAN 2 03h (Processor) FAN 3 These ID are defined in Table 28-11 of IPMI v1.0 specification. This value is programmable because that may be used in add-in-card or connected to other device. The Entity Instance is shown as following. Fan Sensor Entity Instance (default) FAN 1 01h (Main system board) FAN 2 01h (Processor 1) FAN 3 02h (Processor 2) FAN1 : 0Ah FAN2 : 0Bh FAN3 : 0Ch Status Value Status type Description Byte Count 0Bh W83791D/G will respond 0Bh all relative information. When event status index 02h is more than 0Fh, the machine will be ended the transmission.
Entity ID
Entity instance
Event status index
Event status
0000_0010b Deasserted (send) 0000_0011b Asserted (send) 0000_0111b Event Status End
The reference table of ASF 0.64 is shown as following.
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Fan: Get Event Data message, continued.
ASF PACKET DATA
FAN CLOCK INPUT
Event Severity
Monitor (0x01): That is represented the monitored fan count is under the limit count. Critical Condition (0x10): that is represented the monitored fan count is over the limit count.
Monitor (0x01) Upper Speed Fan Speed Lower Speed Critical Condition (0x10)
8.2.4 Case Intrusion: Get Event Data message In the W83791D/G, it has three temperatures for monitoring System Board. The listed table show that have the entity ID, entity instance, event source type, event type, event offset, and so on.
ASF PACKET DATA CASE INTRUSION INPUT
Event sensor type Event type Event offset
05h (Chassis Intrusion) `digital' Discrete (Generic Severity): 03h
(i) 03h: 'digital' Discrete (Generic Severity) 00h: State Deasserted Event Status: 010b (Deasserted, send) Event Status: 011b (Asserted, send) Logic Low Logic High 03h: 'digital' Discrete (Generic Severity) 01h: Asserted (Case Intruded)
Event sensor type: 05h (Case Intruded) Event Type: 03h ('digital ' Discrete, Generic Severity)
Event source type Sensor device
The W83791D/G is complying ASF 1.0 specification and the value is 0 x 68. The ASF specification indicates that the Sensor Device is the SMBus address of the sensor that caused the event for the PET Frame. Therefore, the Sensor Device of the W83791D/G is APR assigned address. The sensor number for case intruded is 11h The Entity ID is 23h for case intruded These ID are defined in Table 28-11 of IPMI v1.0 specification. This value is programmable because that may be used in add-in-card or connected to other device.
Sensor number Entity ID
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Case Intrusion: Get Event Data message, continued.
ASF PACKET DATA
CASE INTRUSION INPUT
Entity instance Event status index Event status
Event Severity
The Entity Instance is 01h for (Main system board) 0x0D (W83791D/G sensor index) Status type Description Status Byte Value Count 0000_0010b Deasserted (send) 0Bh 0000_0011b Asserted (send) W83791D/G will respond 0Bh all relative information. 0000_0111b Event Status End When event status index 02h is more than 0Fh, the machine will be ended the transmission. The reference table of ASF 0.64 is shown as following. Monitor (0x01): That is represented the monitored CASEOPEN is logic Low Critical Condition (0x10): that is represented the monitored CASEOPEN is logic High.
Logic High
Monitor (0x01) Critical Condition (0x10) Logic Low
Case Intruded Input Pin
8.3
ASF Response Registers Index 40h-7Fh (Bank 1)
8.3.1 ASF Upper/Lower Temperature Registers: Generic/Upper/Under temperature
INDEX DESCRIPTION DEFAULT TEMPERATURE
40h 41h 42h 43h 44h 45h 46h-4Eh
Non-critical temperature of temperature sensor 1 setting. Critical Temperature of temperature sensor 1 setting Non-critical temperature of temperature sensor 2 setting. Critical Temperature of temperature sensor 2 setting Non-critical temperature of temperature sensor 3 setting. Critical Temperature of temperature sensor 3 setting Reserved
4Bh (75 Centigrade) 50h (80 Centigrade) 4Bh 50h 4Bh 50h Reserved.
Note: When read index 45h (Bank 1) have to use index 46h (Bank 1).
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8.3.2
4Fh
Sensor device: (SMBus Address, Read/Write)
DESCRIPTION DEFAULT VALUE
INDEX
Sensor Device SMBus Address assigned by ARP
00h
8.3.3
50h 51h 52h 53h 54h 55h 56h 57h 58h 59h 5Ah 5Bh 5Ch 5Dh 5Eh 5Fh 60h
Relative Entity ID Table:
MONITOR ITEM DEFAULT ENTITY ID
INDEX
VIN0 (VCORE) VIN1 (VINR0) VIN2 (+3.3VIN) VIN3 (+5 VIN) VIN4 (+12VIN) VIN5 (-12VIN) VIN6 (-5VIN) VSB VBAT VINR1 FAN1 FAN2 FAN3 Temperature 1 Temperature 2 Temperature 3 Chassis Intrusion Reserved
3 (CPU) 7 (System Board) 7 (System Board) 7 (System Board) 7 (System Board) 7 (System Board) 7 (System Board) 7 (System Board) 7 (System Board) 3 (CPU) 7 (System Board) 3 (CPU) 3 (CPU) 7 (System Board) 3 (CPU) 3 (CPU) 23 (System Chassis) Reserved
61h-6Fh
Table of Entity ID defined in PET 1.0 or IPMI 1.0
ENTITY DEFINITION ENTITY ID
CPU System Memory module System Chassis Fan/Cooling device Memory device
3 7 8 23 29 32
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8.3.4 Entity Instance Register Maximum number of instance is 15
INDEX BIT ENTITY ENTITY INSTANCE (DEFAULT VALUE)
70h 71h 72h 73h 74 h 75h 76h 77h 78h
<7:4> <3:0> <7:4> <3:0> <7:4> <3:0> <7:4> <3:0> <7:4> <3:0> <7:4> <3:0> <7:4> <3:0> <7:4> <3:0> <7:4> <3:0>
VIN0(Vcore) VIN1(VINR0) VIN3 (+5VIN) VIN4 (+12VIN) VIN5 (-12VIN) VIN6 (-5VIN) VIN7(VSB) VIN8(VBAT) VIN9(VINR1) FAN1 FAN2 FAN3 TEMP1 TEMP2 TEMP3 Reserved Chassis
1 (Processor 1_CPU1). 1 (System board 1). 1 (System board 1). 1 (System board 1). 1 (System board 1). 1 (System board 1). 1 (System board 1). 1 (System board 1). 2 (Processor 2_CPU2). 1 (System board 1). 1 (Processor 1_CPU1). 2 (Processor 2_CPU2) 1 (System board 1) 1 (Processor 1) 2 (Processor 2) 0 1 (System Chassis)
VIN2 (+3.3VIN) 1 (System board 1).
The Entity for a given event varies according to what entity the environmental sensor is monitoring. For example, a typical managed system board can have temperature monitoring associated with the system board and with the main processor. Thus, the Entity IDs and Entity Instance values for these would be Entity ID=7, Entity Instance=1 for `main system board' and Entity ID=3, Entity Instance=1 for `processor 1', respectively.
8.4
BJT RT-Table - 50h-57h (Bank 7) TEST mode only
Bank 7 registers 50h-57h are BJT table for Winbond test. User doesn't use these registers.
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9. ELECTRICAL CHARACTERISTICS 9.1 Absolute Maximum Ratings
PARAMETER RATING UNIT
Power Supply Voltage Input Voltage Operating Temperature Storage Temperature
-0.5 to 7.0 -0.5 to VDD+0.5 0 to +70 -55 to +150
V V C C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
9.2
DC Characteristics
PARAMETER SYM. MIN. TYP. MAX. UNIT CONDITIONS
(Ta = 0 C to 70 C, VDD = 5V 10%, VSS = 0V) I/O12t - TTL level bi-directional pin with source-sink capability of 12 mA Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage VIL VIH VOL VOH ILIH ILIL 2.4 +10 -10 2.0 0.4 0.8 V V V V A A IOL = 12 mA IOH = - 12 mA VIN = VDD VIN = 0V
I/O12ts - TTL level bi-directional pin with source-sink capability of 12 mA and schmitt-trigger level input Input Low Threshold Voltage Input High Threshold Voltage Hysteresis Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage VtVt+ VTH VOL VOH ILIH ILIL 2.4 +10 -10 0.5 1.6 0.5 0.8 2.0 1.2 0.4 1.1 2.4 V V V V V A A VDD = 5 V VDD = 5 V VDD = 5 V IOL = 12 mA IOH = - 12 mA VIN = VDD VIN = 0V
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DC Characteristics, continued.
PARAMETER
SYM.
MIN.
TYP.
MAX.
UNIT
CONDITIONS
OUT12t - TTL level output pin with source-sink capability of 12 mA Output Low Voltage Output High Voltage VOL VOH 2.4 0.4 V V IOL = 12 mA IOH = -12 mA
OD8 - Open-drain output pin with sink capability of 8 mA Output Low Voltage VOL 0.4 V IOL = 8 mA
OD12 - Open-drain output pin with sink capability of 12 mA Output Low Voltage VOL 0.4 V IOL = 12 mA
OD48 - Open-drain output pin with sink capability of 48 mA Output Low Voltage VOL 0.4 V IOL = 48 mA
INt - TTL level input pin Input Low Voltage Input High Voltage Input High Leakage Input Low Leakage INts VIL VIH ILIH ILIL 2.0 +10 -10 0.8 V V A A VIN = VDD VIN = 0 V
- TTL level Schmitt-triggered input pin VtVt+ VTH ILIH ILIL 0.5 1.6 0.5 0.8 2.0 1.2 +10 -10 1.1 2.4 V V V A A VDD = 5 V VDD = 5 V VDD = 5 V VIN = VDD VIN = 0 V
Input Low Threshold Voltage Input High Threshold Voltage Hysteresis Input High Leakage Input Low Leakage
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9.3
9.3.1
AC Characteristics
Serial Bus Timing Diagram
t SCL t tR R
SCL
t HD;SDA
t SU;DAT t SU;STO
SDA IN
VALID DATA
t HD;DAT
SDA OUT Serial Bus Timing Diagram
Serial Bus Timing
PARAMETER SYMBOL MIN. MAX. UNIT
SCL clock period Start condition hold time Stop condition setup-up time DATA to SCL setup time DATA to SCL hold time SCL and SDA rise time SCL and SDA fall time
t SCL tHD;SDA tSU;STO tSU;DAT tHD;DAT tR tF
-
10 4.7 4.7 120 5 1.0 300
uS uS uS nS nS uS nS
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10. HOW TO READ THE TOP MARKING
The top marking of W83791D
W83791D 025AA
Left: Winbond logo 1st line: Type number W83791D, D means LQFP (Thickness = 1.4 mm). 2nd line: Tracking code 025 A A 025: packages made in 2000, week 25 A: assembly house ID; A means ASE, O means OSE A: IC revision; A means version A, B means version B The top marking of W83791G
W83791G 025AA
Left: Winbond logo 1st line: Type number W83791G, G means lead-free package. 2nd line: Tracking code 025 A A 025: packages made in 2000, week 25 A: assembly house ID; A means ASE, O means OSE A: IC revision; A means version A, B means version B
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11. PACKAGE SPECIFICATION
(48-pin LQFP)
HD D
36 25
Symbol
Dimension in inch Min. Nom. Max.
Dimension in mm Min.
--0.05 1.35 0.17 0.09
Nom.
----1.40 0.20 --7.00 7.00 0.50 9.00 9.00
Max.
1.60 0.15 1.45 0.27 0.20
37
24
E
HE
48
13
1
e
b
12
A A1 A2 b c D E e HD HE L L1 y 0
Notes:
c
0.45
0.60 1.00
0.75
--0
0.08 3.5
--7
A2 A1 y
A
Seating Plane
See Detail F
L L1 Detail F
1. Dimensions D & E do not include interlead flash. 2. Dimension b does not include dambar protrusion/intrusion. 3. Controlling dimension: Millimeters 4. General appearance spec. should be based on final visual inspection spec.
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VOLTAGE SENSING
CPUVCOA GTLVOLT 3VCC R1 10K R2 10K R3 10K +12VIN +12V R4 28K 1% R6 +5V R 34K 1%/791D 0 /782D R8 5VSB R 5.1K 1%/782D 0 /791D R10 R R9 R7 R R5 10K 1% VINR1 R 50K 1%/791D GNDA R GNDA R R R VCORE VINR0 3VIN
/782D : Only for W83782D /791D : Only for W83791D
3VCC R30 R 4.7K 330 R31 R 4.7K SMDAT SMCLK R33 R 330
SDA SCL
R R32
L1 INDUCTOR FB/791D +5VSB C1 CAP 10u/791D GNDA C2 CAP 0.1u/791D
+5VSB GNDA R 7.5K 1%/782D R11 232K 1% -12VIN R
-12V +5V
56K 1% VREF
L2 INDUCTOR FB/782D
C3 CAP 10u/782D R12 R R13 120K 1% -5VIN ADRMSELIN R R GNDA
C4 CAP 0.1u/782D
-5V R14
VCORE VINR0 3VIN VINR1 +12VIN -12VIN VBAT +5VSB -5VIN GNDA BEEP VID3
56K 1%
3VSB 36 35 34 33 32 31 30 29 28 27 26 25 U1
IRQ/GPIO10
R
VCORE VINR0 +3.3VIN VINR1 +12VIN -12VIN VBAT +5VSB -5VIN GNDA BEEP VID3
0/782D R16 0/791D VREF T3 T2 T1 37 38 39 40 41 42 43 44 45 46 47 48
R15 R 10K/791D R17 24 23 22 21 20 19 18 17 16 15 14 13 VID2 OUT3/VID90 SDA SCL FAN1IN FAN2IN FAN3IN CASEOPEN GNDD VDD C5 VCC SLOTOCC# R 0/791D R19 MR# R 0/782D
R? SMI# R? LED
0 SMI#/LED
R18 FAN4IN 0/791D R22 0/791D R23 FAN5IN 0/791D R24 0/791D (FAN) (FAN)
0/791D
EVNT2/A1
VID0 OVT# SMI#/LED
EVNTRAP5/GPIO9/PWMOUT5 EOP/GPIO11 REXT ADDR/GPIO0 CLKOUT/GPIO1 DATA/GPIO2 CTRL/GPIO3 MODE/GPIO4 SPEAKER/LED/SPEECH_SEL PWMOUT1/A0 PWMOUT2/A1 VID1
(EVNT2)
EVNT1/A2
VREF VTIN3/PIITD3 VTIN2/PIITD2 VTIN1/PIITD1 VID0 OVT# IRQ/GPIO10 SMI#/LEDOUT EVNTRAP1/GPIO5 EVNTRAP2/GPIO6/FANIN4 EVNTRAP3/GPIO7/FANIN5 EVNTRAP4/GPIO8/PWMOUT4
VID2 PWMOUT3/VID_V90 SDA SCL FANIN1 FANIN2 FANIN3 VID4 CASEOPEN SLOTOCC# GNDD VDD
(From PII/PIII CPU)
0: means CPU is present 1: means CPU is absent
VID4
EVNT3/A0
CAP 10u
C6 CAP 0.1u
(EVNT3)
R25 0/791D (EVNT4) R26 R 0/791D (FAN) R27 0/782D R
GNDA
GNDA
GNDD
EVNT4 PWMOUT4
1 2 3 4 5 6 7 8 9 10 11 12
L3 INDUCTOR FB
W83791D
EOP/IOW# REXT/CLKIN ADDR/D7 CKOUT/D6 DATA/D5 CTRL/D4 MODE/D3 SPK/D2 PWMOUT1/D1 PWMOUT2/D0 VID1
SMI#/LEDOUT function circuit
5VSB 3VCC R? 270 TO CHIPSET R20 R 4.7K R21 R 4.7K OVT# R129 0
R28
R29
CS# Select one of the two setting.(FOR 782D) Set A2-A0 as 3 lowest order bits of ISA address bus ADRMSELIN SA2 SA1 SA0 R35 R36 R37 0 0 0 R R R EVNT1/A2 EVNT2/A1 EVNT3/A0
0/791D 0/791D (EVNT5) (FAN)
Beep Circuits
VCC R38 R 100 LS1 R34 EVNT5/IOR# PWMOUT5 220K/ 791D R LED Q? MOSFET N 2N7000 5VSB R? 1K D? LED
{
THRM#
EXTSMI#
SMI#
R39 R 10K
R130 0/791d,B
2
U7A
1
R131 0/791d,B
SMI#
BUZZER Set A2-A0 as bit2, bit1, bit0 of 7 bit I2C address setting VCC IA2 IA1 IA0 ADRMSELIN R41 R42 R43 0 0 0 R R R EVNT1/A2 EVNT2/A1 EVNT3/A0 BEEP R40 R 510
!!Only for 791D ver B.
7404 /791d, B
Q1 NPN 3904
WINBOND ELECTRONICS CORP. Title
W83782D-W83791D Application Circuit Rev 0.2 Sheet 1 of 5
Size Document Number Custom Date: Tuesday, May 22, 2001
- 88 -
Publication Release Date: April 14, 2006 Revision 1.1
W83791D/G
Temperature Sensing
RT1
PWM Circuit for FAN1-3 speed control
VSB R44 4.7K R46 1K Q3 PWMOUT1/D1 R51 R 0 MOSFET N 2N7002 R R Q2 PNP 3906 C7 47u + JP1 3 2 1 HEADER 3 D1 DIODE 1N4148 +12V 10K 1% R45 R 47K/791D
VREF
R47
R
T
(for system)
10K 1% R49 R
THERMISTOR RT2
R48 R 4.7K R50 27K R R52 R 10K FAN1IN
T
10K 1%
(for cpu1) (for cpu2)
10K 1% R53 R
THERMISTOR RT3
T
10K 1%
10K 1% T1 T2 T3
THERMISTOR
R45,R61 in order to trap address be A0=1,A1=0
GNDA R54 4.7K R55 1K Q5 PWMOUT2/D0 R60 30K 1% CAPACITOR C9 3300p R R58 R 0 D+ MOSFET N 2N7002 R R Q4 PNP 3906
+12V
Measuring CPU temperature by either thermistor or diode.
VREF T2 GNDA
D2 DIODE 1N4148 JP2 + C8 47u 3 2 1 HEADER 3
R56 R 4.7K R57 27K R R59 R 10K FAN2IN
(from PII/PIII CPU)
D-
R61 R 47K/791D
+12V R63 R RT4
T
10K 1%
R62
R R Q6 PNP 3906 JP3 + C10 47u 3 2 1 HEADER 3 D3 DIODE 1N4148
VREF
10K 1%
THERMISTOR
(for cpu2)
4.7K R64 1K
T2
GNDA OUT3/VID90 R67 R 0
R65 R 4.7K R66 27K R R68 R 10K FAN3IN
Q7 MOSFET N 2N7002
PWM Circuit for FAN4-5 speed control when select these pin to PWMOUT/FAN function
+12V R69 4.7K R70 1K R75 PWMOUT4 Q9 R 0 MOSFET N 2N7002 R R Q8 PNP 3906 JP4 + C11 47u 3 2 1 HEADER 3 D4 DIODE 1N4148
Select VID Table
R71 R 4.7K R73 27K R R76 R 10K FAN4IN R72 VSB R 47K /791D R74 47K /791D R OUT3/VID90 OUT3/VID90
Select one of the two VID Table setting. 0:Old VID Table(VRM 8.3) 1:New VID Table(VRM 9.0)
+12V R77 4.7K R78 1K R81 PWMOUT5 Q11 R 0 MOSFET N 2N7002 R R Q10 PNP 3906 JP5 + C12 47u 3 2 1 HEADER 3 D5 DIODE 1N4148
R79 R 4.7K R80 27K R R82 R 10K FAN5IN WINBOND ELECTRONICS CORP. Title
W83782D-W83791D Application Circuit Rev 0.2 Sheet 2 of 5
Size Document Number Custom Date: Tuesday, May 22, 2001
- 89 -
Publication Release Date: April 14, 2006 Revision 1.1
W83791D/G
CPU Voltage ID input/output
3VCC R83 R 10K R84 R 10K R85 R 10K R86 R 10K R87 R 10K
Circuits for 782D
EVNT5/IOR# IOR# IOW# CLKIN VID4 VID3 VID2 VID1 VID0 R88 R R89 R R90 R R91 R R92 R R94 R R96 R R98 R R100R R102R R103R 0 0 0 0 0 0 0 0 0 0 0 EOP/IOW# REXT/CKLIN ADDR/D7 CKOUT/D6 DATA/D5 CTRL/D4 MODE/D3 SPK/D2 PWMOUT1/D1 PWMOUT2/D0
PIIVID4 PIIVID3 PIIVID2 PIIVID1 PIIVID0
R93 R95 R97 R99 R101
1K 1K 1K 1K 1K
SD[0..7] VID0 VID1 VID2 VID3 VID4
(From CPU)
}
To Power Regulator
Case Open Circuits
R104 R R106 R 2M/782D R109 R 0/782D S1 CASEOPEN SW 0/782D VBAT R105 R 0/791D C13 CAP 1000p /791D CASEOPEN R110 R 0/791D R111 R 2.2M/791D 74HC14 /791D U2B 4 3
These two inverters consume VBAT
74HC14 /791D U2A 1 2
R107 R 10K/791D
R108 R CASEOPEN 0/791D
WINBOND ELECTRONICS CORP. Title W83782D-W83791D Application Circuit Size B Date: Document Number Tuesday, May 22, 2001 Sheet 3 of 5 Rev 0.2
- 90 -
Publication Release Date: April 14, 2006 Revision 1.1
W83791D/G
Select SPEECH / LED Function by one of three cricuits. / 791D
1.
VCC
C14 SPK/D2 R112 510 1uF/16V
2.
3.
R113 270
VCC C15 LINE_OUT_L LS2 1uF/16V R114 8 ohm SPEAKER SPK/D2 R115 510 C17 0.1uF Q12 NPN 8050D LINE_OUT_R 1uF/16V R116 470K C19 100pF C16 100pF
J1
D6 LED
From AC' 97 Codec (W83971D)
470K
LINE_OUT
SPK/D2
Q13 MOSFET N 2N7000
C18
(LED FUNCTION)
(SPEECH FUNCTION)
(SPEECH FUNCTION)
Connect to serial FLASH EEPROM (W55FXX) /791D
VCC R117 EOP/IOW# 0/791D
VCC
R118 EOP/IOW# CTRL/D4 R120 R124 ADDR/D7 0/791D 0/791D 0/791D 1 2 3 4
U3 EOP CTRL VSS ADDR MODE VDD CLK DATA W55F10 8 7 6 5
R119 0/791D
MODE/D3 U4 1 0/791D 2 3 ADDR/D7 R127 0/791D 4 8 7 6 5
R121 MODE VDD CLK DATA W55F10 0/791D MODE/D3 0/791D CKOUT/D6 R126 R128 0/791D DATA/D5 1 2 3 4
U5 EOP CTRL VSS ADDR MODE VDD CLK DATA W55F10 8 7 6 5 1 2 3 4
U6 EOP CTRL VSS ADDR MODE VDD CLK DATA W55F10 8 7 6 5
0/791D CKOUT/D6 R122 CTRL/D4 R125 0/791D DATA/D5
R123
EOP CTRL VSS ADDR
Connect 1 FLASH
Connect 2 or more FLASH
WINBOND ELECTRONICS CORP. Title W83782D-W83791D Application Circuit Size Document Number Custom Date: Tuesday, May 22, 2001 Sheet 4 of 5 Rev 0.2
- 91 -
Publication Release Date: April 14, 2006 Revision 1.1
W83791D/G
REV 0.1 0.15 0.16
Decription First Publication
Add FAN/PWMOUT4-5 circuit Change R34 connect to 5VSB 1. Change R32/R33 value to 330 ohm 2. Modify R34 value as 220K ohm 3. Change SMI# (pin 44) circuit. This update is for B version. Update Pin44 (SMI#/LEDOUT) circuit. This update is for C version.
0.17
0.2
WINBOND ELECTRONICS CORP. Title Size A Date: W83782D-W83791D Application circuit Document Number Tuesday, May 22, 2001 Sheet 5 of 5 Rev 0.2
- 92 -
Publication Release Date: April 14, 2006 Revision 1.1
W83791D/G
Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owner
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
- 93 -
Publication Release Date: April 14, 2006 Revision 1.1

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